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Senior Staff Engineer, CAD - Packaging Group

Synopsys
United Statesfull_timeVerifiedPosted 22 May 2025
💰 $207,000/yr($138,000/yr$207,000/yr)

About the role

General Information

Job Title Senior Staff Engineer, CAD - Packaging Group Job ID 10662 City Sunnyvale State/Province California Date Posted 11-Apr-2025 Job Category Engineering Job Subcategory CAD Engineering Hire Type Employee Base Salary Range: $138000 - $207000

Descriptions & Requirements

Job Description and Requirements

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly skilled and experienced engineer with a deep understanding of System-on-Chip (SoC) and IP architecture. With a background in CAD engineering and signal integrity, you are passionate about developing and implementing advanced methodologies and technologies. You thrive in collaborative environments, working closely with technical leaders and customers to deliver innovative solutions. You have a strong foundation in ASIC implementation techniques and chip assembly methodologies, and you excel in technical leadership roles. Your expertise in signal integrity fundamentals, packaging designs, and scripting in Unix/Linux environments sets you apart. You are dedicated to continuous learning and staying abreast of new technologies and tools in the semiconductor industry.

What You’ll Be Doing:

  • Developing and implementing SoC/IP flows and methodologies for signal and power integrity and advanced packaging architecture.
  • Utilizing Ansys Multi-Physics tools and scripting design flows around tools like HFSS, SiWave, Redhawk for EM-IR (both static and dynamic), and Redhawk for thermal analysis.
  • Conducting PDN analysis and generating CPM models, performing chip-package-PCB system simulations in both time and frequency domains.
  • Preparing design flows and methodologies with a strong understanding of PCB, packaging, and RDL designs.
  • Collaborating with other Synopsys teams, including BU AEs and sales, to develop and deploy packaging and signal integrity solutions.
  • Ramping up on new 3DIC packaging and SI tools and methodologies using Synopsys products to enable customers.

The Impact You Will Have:

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Company

Synopsys

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