Digital Design Lead

<p><strong>Role Summary</strong></p> <p>We are seeking experienced Digital Design Leads to drive RTL design and verification for next-generation semiconductor products. This role leads the digital design effort across high-speed interface and memory subsystem IPs, partnering with architecture, verification, and physical design teams to deliver silicon-ready designs.</p> <p>&nbsp;</p> <p>Key Responsibilities</p> <ul> <li>Lead RTL design and micro-architecture definition for digital IP blocks from concept through tape-out.</li> <li>Own design of Ethernet and/or PCIe controller/PHY digital logic, ensuring compliance with relevant industry specifications.</li> <li>Design and integrate memory sub-system IP, including DDR, HBM, and/or LPDDR controllers and PHYs.</li> <li>Implement and optimize Forward Error Correction (FEC) logic for high-speed serial links.</li> <li>Drive design reviews, timing closure, and low-power design practices in collaboration with cross-functional teams.</li> <li>Mentor junior design engineers and coordinate with verification, DFT, and physical design teams to meet project schedules.</li> </ul> <p>&nbsp;</p> <p>Required Skills &amp; Experience</p> <ul> <li>Proven track record as an RTL Design Lead on complex digital ASIC/SoC projects.</li> <li>Hands-on experience with Ethernet and/or PCIe protocol design (controller and/or PHY level).</li> <li>Experience with Memory Sub-systems: DDR, HBM, and/or LPDDR controller/PHY design and integration.</li> <li>Working knowledge of Forward Error Correction (FEC) schemes as applied to high-speed SerDes links.</li> <li>Strong RTL coding skills (Verilog/SystemVerilog) and familiarity with standard ASIC design flows.</li> <li>Experience with timing closure, low-power design, and design-for-test (DFT) considerations.</li> <li>Strong communication skills and experience leading or mentoring design teams.</li> </ul> <p>&nbsp;</p> <p>Qualifications</p> <ul> <li>Bachelor's or Master's degree (BS/MS) in Electrical Engineering, Computer Engineering, or a related field.</li> <li>Relevant years of hands-on RTL design experience in the semiconductor industry (leadership experience preferred).</li> </ul><div class="content-pay-transparency"><div class="pay-input"><div class="title">California Pay Range</div><div class="pay-range"><span>$180,000</span><span class="divider">&mdash;</span><span>$200,000 USD</span></div></div></div>