The application window is expected to close on: 08/07/2026

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team:

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. 

Your Impact:

We are looking for a motivated technical leader to join the CAD/Methodology team. You will own Infrastructure engagement and alignment including the arrangement/QA for Vendor IPs, standard cells and Process Design Kits (PDKs)—from early architecture through tape-out and into post-silicon bring-up and debug.

 

Success depends as much on clarity and follow-through as on depth in flows and tools. You will be the primary key stakeholder bridging between Cisco projects leads and all supply chain dependencies such as IP/std cells vendors and external foundries.

Responsibilities include keeping schedules, aligning technical requirements, and aligning delivery commitments so IP and PDK land on time, qualified, and usable in Cisco projects. 

Key Responsibilities:

• Stakeholder leadership and communication — Partner routinely with Program/Project Management, Physical Design, Package / SI, RTL/Design, Design Verification, and CAD/Methodology. Translate priorities across disciplines, surface risks early, and drive decisions.
• External engagement and IP delivery — Work with foundries and IP vendors on roadmaps, releases, and bug fixes.
• Vendor IP and PDK lifecycle — Manage vendor deliverables end-to-end including integration, validation, qualification, versioning, and controlled distribution into the design environment.
• Help define and evolve the installation, QA, and release platform for IPs and PDKs.
• Collaborate with design teams on benchmarking vendors and technology options where trade-offs affect PPA, schedule, or flow risks, support informed choices for programs.
• Foundry collateral quality — Evaluate, integrate, and debug PDKs, technology files, and libraries for flow compatibility and design-rule readiness, feed issues back to vendors with clear technical context.
• Documentation enablement for IP/PDK usage, integration, and best practices.

 

Minimum Qualifications:

• 8+ years in physical design enablement, CAD, or equivalent, with prior experience with ASIC flows, physical design methodologies, and foundry processes.
• Prior experience in communication and program management.
• Prior experience with multi-party threads, writing summaries for executives and engineers, and keep pre-silicon and post-silicon stakeholders aligned.
• Prior experience with IP installation, PDK enablement, and technology file management.

 

Preferred Qualifications:

• Scripting (e.g., Python, TCL) for automation; comfortable with process nodes and PDK structures in real programs.
• Hands-on experience with timing models.
• Familiarity with EDA tools (e.g., Synopsys, Cadence, Siemens) for physical design and verification.

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.