Principal Engineer, CPU Architecture & Performance Research

<div class="content-intro"><p><span style="font-size: 12pt;"><strong>Please Note:</strong></span></p> <p>To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.&nbsp;</p> <p><span style="font-size: 12pt;"><strong>Advancing the World’s Technology Together</strong></span></p> <p>Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.&nbsp;</p> <p>We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.</p></div><p>&nbsp;</p> <p><strong>Principal</strong><strong>,</strong><strong> CPU Architecture &amp; Performance </strong><strong>Research </strong><strong>Engineer</strong></p> <p><strong>What You’ll Do</strong></p> <p>Architecture Research Lab is seeking Principal CPU Architecture &amp; Performance Engineer to lead the definition, analysis, and optimization of next-generation CPU microarchitectures (RISC-V core). This role is focused on end-to-end performance: from architectural trade-offs and workload characterization to micro-architectural modeling, simulation, and silicon bring-up correlation.</p> <p>You will work closely with architecture, design, compiler, and system teams to drive performance and efficiency across a broad set of real-world workloads</p> <p><strong>Location:</strong> Daily onsite presence at our San Jose office in alignment with our Flexible Work policy</p> <p>Job ID: 42918</p> <ul> <li>Define and evaluate CPU micro-architectural features for future cores (frontend, execution engine, memory hierarchy, interconnect).</li> <li>Lead performance analysis using simulators, RTL.</li> <li>Help develop and validate performance models (cycle-accurate, trace-driven, statistical).</li> <li>Characterize workloads (SPEC, server, client, AI/ML, cloud, internal traces) and translate findings into architectural requirements.</li> <li>Identify performance bottlenecks and propose data-driven optimizations.</li> <li>Drive architecture-to-implementation alignment with design team.</li> <li>Collaborate with compiler, OS, and system architects on cross-stack performance is