Sr. Principal Electrical Engineer - FPGA/ASIC Team (Onsite)

Date Posted:

2026-07-17

Country:

United States of America

Location:

US-IA-CEDAR RAPIDS-121 ~ 350 Collins Rd NE ~ BLDG 121

Position Role Type:

Onsite

U.S. Citizen, U.S. Person, or Immigration Status Requirements:

U.S. citizenship is required, as only U.S. citizens are authorized to access information under this program/contract.

Security Clearance Type:

None/Not Required

Security Clearance Status:

Not Required

At RTX, the world's largest aerospace and defense company, 185,000 great minds are united by purpose and inspired to make a difference solving the world’s most complex problems. With our three market leading businesses, world-class operations and investments in research and development, we offer capabilities and opportunity no one else can. Together, we push the boundaries of known science and find new ways to connect and protect our world.

Collins Aerospace is a leader in technologically advanced, intelligent solutions that help redefine the aerospace and defense industry. With a comprehensive portfolio and deep technical expertise, we help customers meet the demands of the global market. Join us and help shape the future of aerospace and defense.

Become part of a growing Avionics FPGA/ASIC team.  This position is for a highly experienced, highly motivated Electrical or Computer Engineer that will be involved in the design, implementation, verification and integration of a wide variety of high-performance ASICs, FPGAs, and SoPCs for Collins Avionics solutions. As an engineer in this organization, you will be employing best practice design and verification methodologies supporting our legacy and next generation Displays, Computing, and Networking Products.

What You Will Do:

• Requirements capture, decomposition, and traceability.

• ASIC/FPGA/SoPC digital architecture development and design.

• Develop RTL design code and simulation in VHDL, Verilog, and/or SystemVerilog.

• Create UVM constrained random environments using SystemVerilog.

• Create placement and timing constraints.

• Perform synthesis, place and route.

• Perform static timing analysis, linting analysis, LEC, and clock-domain-crossing analysis.

• Perform ASIC/FPGA/SoPC verification using inspection, analysis, simulation, and test methods.

• Creation of DO-254 DAL-A certification artifacts for Airborne Electronic Hardware (AEH).

• Conduct and/or participate in peer reviews throughout product lifecycle.

• Participate in FAA SOI audits.

• Create engineering bids and support RFIs and RFPs.

• Communicate well with a wide variety of individuals including Engineering, Program Management, internal leadership and customers.

• May perform the duties of a project engineer.

• Recommend new tools and practices for continuous improvement in the group’s ASIC/FPGA design flow.

• Provide guidance or mentor other engineers with a variety of skills and backgrounds.

Qualifications: You Must Have:

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 10 years prior relevant experience or an Advanced Degree in a related field and minimum 7 years of experience

• Experience writing RTL and test benches using VHDL, Verilog, or SystemVerilog.

• Experience using FPGA specific tools (e.g. Questasim, Vivado, Libero, Synplify Pro, etc.).

• Experience with data interfaces (PCIe, DDR, I2C, Ethernet, CDN, ARINC-429, etc.).

• Experience with device level timing and clock domain crossing.

• Experience with Linux (or Unix), scripting, C/C++, Python, and/or Perl.

• Ability to work with minimal supervision, as part of a team of engineers with a variety of skills and backgrounds, located throughout the world and matrixed into projects with aggressive schedules and frequent milestones.

Qualifications We Prefer:

• Experience with UVM Constrained Random Methodology.

• Experience with DO-254 processes and design assurance activities for ASIC, FPGA, and/or SoPC developments.

• Experience with video and/or networking concepts and architectures.

• Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, code coverage, LEC, SystemVerilog).

• Experience successfully managing cost, schedule, and performance objectives.

• Basic risk management skills