Mid to Sr. FPGA Engineer

Mid to Sr. FPGA Engineer

Job Category: Engineering

Time Type: Full time

Minimum Clearance Required to Start: None

Employee Type: Regular

Percentage of Travel Required: None

Type of Travel: None

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CACI's Mastodon Design team in Rochester, NY specializes in designing and building hardware and software to meet our customers’ next requirement. We focus on offering devices that can be fielded immediately to meet the mission needs that lie directly ahead. Size, weight, power, and packaging are of paramount importance in everything we design and build. Our expertise allows us to rapidly provide these solutions in specialized electronic/mechanical design, embedded & application-level software, reverse engineering & protocol analysis, and RF signals and communications systems. U.S. Citizenship required.  Successful candidates must be willing and able to obtain a security clearance.

We are seeking a FPGA Engineer to work on the development of our wireless product line.  This role requires understanding of both theoretical and practical aspects of designing FPGA solutions for RF products. An ideal candidate will have demonstrable experience designing such solutions in a commercial environment with aggressive time-scales. 

Qualifications:

• BS in EE or similar field and experience in designing DSP/FPGA solutions 
• 5+ years of relevant experience 
• Ability to obtain and maintain minimally a Secret clearance 
• In-depth understanding of HDL coding in VHDL, Verilog and System Verilog 
• Pin and Timing Constraints management 
• Demonstrated ability to debug complex FPGA designs in system 
• Ability to implement and debug complex high-speed architectures like JESD204C, 2.5G, 10G, 40G, 100G Ethernet. 
• Ability to implement and debug VITA-49 transport layer in a system. 
• Communications systems, associated algorithms and their design. This includes an understanding of RF filters, signal modulation/demodulation, channel equalization/channel estimation, channel coding (FEC), RF signal acquisition, RF frequency control (AFC), RF gain control (AGC) 
• DSP baseband signal processing and task scheduling 
• DSP Peripheral programming and control 
• Programming DSP and FPGA devices using Python, C/C++, MATLAB/Simulink and VHDL 
• Self-starter who likes working in a team environment 

Nice to have Qualifications:

• Interpreting and implementing wireless standards such as 3GPP (LTE, WCDMA, GSM), IEEE 802.11 (WIFI) and IEEE 802.15 (UWB, Zigbee) 
• Mixed signal requirements including quantization bits, dynamic range (SFDR), power consumption and the design of baseband equivalent models. Experience designing solutions to overcome imperfections in the RF signal path 
• Demonstrated ability in bringing up custom hardware with FPGAs or SoCs 
• Experience with SoC’s such as Ultrascale +, Zynq 7000, Agilex, etc. 
• Experience with softcore processors such as Picoblaze, Microblaze, NIOS 
• Experience with DMA and AMBA Buses such as AXI/AXIS and ACP 
• Simulation experience – Understanding of abstracted SystemVerilog classes and packages 

This position is contingent on funding and may not be filled immediately. However, this position is representative of positions within CACI that are consistently available. Individuals who apply may also be considered for other positions at CACI.

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What You Can Expect:

 

A culture of integrity.

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