Micro-Architect and RTL Designer

<p><strong>What MatX Is Building</strong></p> <p>MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.</p> <p><strong>What You'll Do Here</strong></p> <ul> <li>Contribute to MatX’s silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design</li> <li>Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design</li> <li>Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout</li> <li>Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results</li> </ul> <p><strong>Who You Are</strong></p> <ul> <li>Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon&nbsp;</li> <li>4 years or more experience with SystemVerilog, Python, C/C++ and similar scripting and programming languages for chip design and related flows</li> <li>Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities&nbsp;</li> <li>Experience with testing your designs and working closely with verification teams towards performance and coverage closure goals</li> <li>Hands-on experience with design synthesis, design lint, and related flows to take designs to high quality sign-off</li> <li>Familiarity with verification, emulation platforms and methodologies is a plus</li> <li>Experience with high speed I/O IP is a plus</li> <li>A lot of experience with logic that focuses on moving, storing, or managing data such as caches, buffers, crossbars, etc… is a plus</li> <li>This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday</li> </ul> <p><strong>Compensation</stro