About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

About Marvell
Marvell’s semiconductor solutions are the essential foundation of the data infrastructure connecting our world. From enterprise and cloud to AI, automotive, and carrier networks, our technologies power the systems driving tomorrow’s innovation. At Marvell, you can shape industries, influence the direction of next-generation architectures, and drive meaningful, enduring technological impact.

Your Team, Your Impact
As Senior Director of Systems Architecture within Marvell’s Enterprise Networking Business unit, you will be the strategic technical leader guiding the direction and customer adoption of Marvell’s industry-leading Ethernet PHY, SerDes, and retimer products across 1G–200G+ segments.
You will set the architectural vision for customer engagements, drive key design wins at Tier-1 hyperscale, enterprise, and carrier accounts, and ensure the successful production ramp of complex high-speed connectivity solutions. You’ll influence product roadmap, own critical executive-level technical relationships, and serve as one of Marvell’s most senior external technical voices.

What You Can Expect

What We’re Looking For

Required

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 20+ years of experience in high-speed connectivity, Ethernet PHY, SerDes, optical modules, mixed-signal ICs, or related system architecture roles.

• Demonstrated success leading architecture or applications organizations supporting Tier-1 enterprise, cloud, or hyperscale accounts.

• Deep expertise in high-speed board design, signal integrity, system modeling, and debug methodologies.

• Strong lab and system-level hands-on experience (oscilloscopes, protocol analyzers, traffic generators).

• Proven ability to communicate technical strategy at the executive level and influence both internal and external organizations.

• Strong background in C/C++, Python/TCL scripting, automation frameworks, and system-level diagnostics.

• Experience driving cross-functional teams and managing multiple strategic customer programs.

• Willingness to travel globally.

Preferred

• Prior leadership of architecture, systems engineering, or applications engineering organizations.

• Experience defining semiconductor product roadmaps or participating in technical standards bodies.

• Background in technical sales strategy, solution architecture, or executive-level customer engagement.

• Experience driving development of next-generation connectivity technologies (e.g., 112G/224G SerDes, emerging PHY standards, optical integration).

What We're Looking For

What You Can Expect

Strategic Technical Leadership

• Serve as the executive technical authority for high-speed connectivity architectures, guiding global customer strategy and ensuring alignment across Marvell’s silicon, firmware, systems, and marketing organizations.

• Define system-level architectures for next-generation PHY/SerDes/retimer solutions and ensure successful deployment across enterprise, cloud, AI, and carrier markets.

• Represent customer technology requirements and long-term trends to Marvell leadership to influence multi-year product and roadmap planning.

Customer Architecture Engagement

• Lead high-level technical engagements with CTO, Chief Architect, and Distinguished Engineer counterparts at global Tier-1 customers.

• Translate complex customer requirements into scalable, manufacturable system architectures utilizing Marvell’s connectivity portfolio.

• Oversee architecture reviews, high-speed PCB design guidance, signal integrity strategies, system-level debugging, and executive technical escalations.

Product & Roadmap Definition

• Partner closely with silicon architects, engineering leaders, and product management to influence next-generation PHY and SerDes product definitions, standards participation, and ecosystem stra