Senior Design Verification Engineer

SENIOR DESIGN VERIFICATION ENGINEER

We are seeking a motivated SR ASIC Verification Engineer to join our dynamic team. The ideal candidate should possess strong analytical and problem-solving skills and be eager to learn and grow within the field of ASIC verification.

 We welcome candidates who are eager to expand their skills and knowledge in ASIC verification and contribute to exciting projects in a supportive environment. If you have a passion for technology and a desire to excel in your career, we encourage you to apply!

KEY RESPONSIBILITIES

• Familiarity with UVM, System Verilog, and C or C++
• Experience with System Verilog simulators and waveform debuggers
• Exposure to developing and executing test plans for Unit/IP/Subsystem/SOC level verification
• Experience in System Verilog test bench development, including stimulus, checkers, transactors/BFMs, assertions, and cover points
• Ability to identify bugs in architecture, functionality, and performance, along with strong overall debug and analytical skills
• Exposure to design and verification tools such as VCS or equivalent simulation tools
• Understanding of Computer Architecture concepts

PREFERRED QUALIFICATIONS

• Strong analytical and problem-solving skills
• Excellent debugging capabilities
• Ability to work collaboratively in a team environment and communicate effectively with peers
• BSEE or equivalent. MSEE preferred