Senior Physical Design Engineer

Microsoft Silicon, Cloud, Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to develop new generation silicon is of paramount importance. To achieve this goal, Microsoft’s Cloud Compute Development Organization (CCDO) is seeking a passionate, driven and intellectually curious engineer to join our silicon hardware physical design team, covering RTL to GDS methodology, design convergence, and design quality for our projects. We are responsible for delivering cutting-edge, CPU-based custom SOC designs that can perform complex and high-performance functions in the most efficient manner. This team will be involved in numerous projects within Microsoft developing CPU based SOCs silicon for data centers. We are looking for a Senior Physical Design Engineer to join the team.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

Responsibilities

• Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification.
• Responsible for Timing & Power critical IPs’ execution with PPA (Power, Performance and Area) focused.
• Responsible for RTL to GDS implementation in Physical Design domain.
• Coordinate with CAD, RTL/Design teams, Architecture team, Power& Performance team, Technology team & other internal/external partners.
• Lead & Influence in TFM (Tools, Flows, and Methodology) & PPAS (Power, Performance, Area & Schedule) for design construction to signoff.
• Demonstrate technical expertise across various domains of Physical Design & Timing Signoff (E2E).
• Clear communications on project status & planning.
• Collaborate across various geographic locations based on need.
• Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.
• Embody our culture and values.

Qualifications

Required Qualifications:

• 7+ years of related technical engineering experience

  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 7+ years of experience in semiconductor design.

Other Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check:
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