Principal Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.  

We are looking for a Principal Design Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team.
 
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Responsibilities

• Own and drive the development of microarchitecture and RTL design, coding, and verification of complex IP blocks, including:

• • Mixed-signal IPs

  • High-speed interfaces

  • Die-to-Die (D2D) communication links

• Ensure IP designs meet stringent power, performance, and timing goals.

• Develop constraints, power intent, synthesis, and perform static checks such as:

  • LINT

  • CDC (Clock Domain Crossing)

  • DRC (Design Rule Checking)

• Develop basic test benches.

• Support verification, DFT (Design for Test), and post-silicon validation activities in collaboration with verification and product teams.

• Collaborate effectively with:

  • Architects

  • Analog mixed-signal designers

  • Verification engineers

  • Physical design and DFT teams

  • Other front-end designers

• Align development methodologies with broader teams.

• Drive continuous improvement of RTL development processes for scalable execution.

Qualifications

Required/minimum qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
• 7+ years of experience in Digital Design, encompassing microarchitecture specification, RTL coding (Verilog/SystemVerilog), CDC/Lint closure, synthesis, timing constraints, PPA trade-offs, post-silicon debug, and successful delivery of IP and ASIC/SoC designs.
• 7+ years of experience in high-speed digital design and Die-to-Die (D2D) interfaces, including clocking, serialization, and signal integrity considerations. 
• 7+ years of experience with automation using scripts PERL, Python or similar  

Other Requirements 

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. 

• This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administr