CPU Microarchitect, Vector and Matrix Compute

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>Tenstorrent is seeking an experienced CPU Architect/Micro-Architect to drive the next generation of high-performance RISC-V CPU Vector (RVV), Floating Point, and Matrix extensions. In this role, you will drive both the architecture and micro-architecture of compute execution units and subsystems that enable the efficient execution of modern high-performance computing (HPC), and AI inference/training workloads.&nbsp;Working closely with architects, software teams, silicon designers, and external IP partners, you will translate HPC/AI workload requirements into scalable CPU architectures that optimize performance, power, and area (PPA) while enabling future HPC/AI computing platforms.&nbsp;This role is ideal for an architect/micro-architect who enjoys working across hardware and software boundaries, defining next-generation compute architectures, and shaping how CPUs and HPC/AI workloads work together.</p> <p>This role is<strong>&nbsp;</strong>remote, based out of North America or Spain.</p> <p>We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</p> <p>&nbsp;</p> <p><strong>Who You Are</strong></p> <ul> <li>Passionate about designing next-generation compute architectures for AI, HPC, and large-scale datacenter systems.</li> <li>Experienced in CPU architecture with strong knowledge of AI acceleration, matrix math, floating point, and heterogeneous compute systems.</li> <li>Comfortable making architectural decisions across CPU cluster and subsystems.</li> <li>Collaborative technical leader who enjoys influencing cross-functional engineering teams.</li> <li>Curious and driven to solve challenging performance, scalability, and system architecture problems.</li> </ul> <p><strong>What We Need</strong></p> <ul> <li>5+ years of experience in CPU design for high-performance computing and AI acceleration.</li> <li>Experience designing hardware for matrix floating-poi