Director, Engineering DFT/DFM

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the wireless networking revolution. Through our broad technology expertise and one of the most extensive product portfolios in the industry, we are Connecting Everyone and Everything, All the Time.

At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management, and the freedom to make meaningful contributions in a setting that encourages creative thinking. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together are changing the way the world communicates.

Requisition ID: 75609 

Job Description

The MSB Director DFT/DFM owns the end-to-end design quality strategy for MSB’s highly integrated RF front-end modules - power amplifiers, LNAs, CMOS controllers, SOI switches, duplexers, and laminate MCMs. From initial concept and architecture definitions through high-volume production, you will:

• Architect and enforce Design For Test (DFT) and Design For Manufacturing (DFM) methodologies
  • Establish required checklists, templates and automations at each level(IP/Block Level/Module Level) for a cohesive DFT/DFM design flow
• Drive IP design teams to ensure IP manufacturability and testability
  • Ensure process and temperature compensations strategies/circuits are in place
  • If trimming is applied, ensure dynamic range is available to meet required compensation
  • Vet new technology to ensure it is fully ready for customer ramps
    • e.g., in new foundry technology such as N40 or SiGe ensure we have statistical confirmation of fuse and POR performance
    • e.g., in new foundry technology such as N40 or SiGe ensure we have proven all IP/library cells that are released
  • DFMEA Mindset: “How can this IP fail?” – stress-test design assumptions
• Drive block level design teams (e.g., ASM/PA/LNA) to ensure block assembly manufacturability and testability
  • Proper sharing of grounds is considered
  • Block level corners are defined, and proper compensations strategies/circuits are in place
• Drive module design teams to ensure module level manufacturability and testability
  • Understand the architecture and work with the test/product/characterization teams for 100% test coverage
• Collaborate with the design and customer quality teams to ensure that lifetime testability is considered at both the circuit and architecture levels
• Install a disciplined RMA / failure-analysis workflow
  • Establish an RMA/design issues lessons learned database with feedback designed to document, communicate, and ensure  zero recurrence
• Build and mentor a high-caliber engineering team embedded with our module design teams to deliver zero-defect designs and rapid high yield ramps

Success in this role demands exceptional cross-functional leadership, deep RF engineering expertise, and clear, timely communication across multiple sites and disciplines.

Responsibilities

Design-In Quality & Validation

• Define, lobby for and enforce DFT/DFM methodologies and checklists at each module phase (Architecture/DEV/P0/P1)
• Drive periodic ATE and FI yield and coverage reviews at each module phase (DEV/P0/P1)
• Ensure early comprehensive ATE coverage
  • Drive to 100% coverage of customer GBT module specifications.
  • Collaborate with Product and Test teams to ensure test coverage and roadmaps are defined clearly for each module
• Specify and deploy new or unique test capabilities (ET metrics, OOB rejection, harmonic coverage) when required
• Drive robust trim algorithm documentation and execution.
  • Our modules have trimmable features using fusing at ATE for device level optimization, eg bias, temp sensor
  • Develop a seamless process to ensure design optimization inputs are documented, communicated, executed and validated at product test
• Ensure robust die-probe plans are defined early and executed with a determined timeline
• Lead statistical vetting of new technology nodes, new materials and newly released IP.
• Corner validation
  • Define and map out validation strategies for device corner conditions and stresses
  • Define and map out validation strategies for customer extreme use cases such as ET calibration, ANT open conditions, XCVR OOB spurious signals
  • Ensure lessons learned from past RMAs and ramp issues as