Senior Principal SERDES Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Marvell post silicon validation group designs and develops test platforms for validating enterprise, cloud, AI, automotive, and carrier architectures including multi-core Arm-based Network processors. The electrical characterization team is a post silicon validation sub-group focused on the debug and characterization of SerDes and DDR interfaces on the processor. The SerDes interface use NRZ and PAM4 signaling for Ethernet, CPRI, JESD, and PCIe interfaces. DRAM interfaces include LPDDR5, DDR4/5 memory modules.

Characterization engineers are responsible for developing test platforms used and automated test suites to characterize the analog interfaces over process voltage and temperature (PVT) extremes to determine silicon viability for volume production.

What You Can Expect

Marvell is seeking a Senior Principal SERDES Signal Integrity Engineer to lead SERDES IP validation for next-generation high-performance compute and storage solutions. This role is critical in shaping Marvell’s leadership in Ethernet IEEE 802.3dj and PCIe Gen6 technologies—interfaces that define the future of hyperscale data centers and AI infrastructure.

The ideal candidate will have expertise in signal integrity, board-level knowledge, SERDES architecture and measurement methods, especially for Ethernet and PCIe interfaces. The position requires a strong background in characterization and design of SERDES IP with special consideration for direct experience in the processors industry. The candidate must have in depth knowledge of the instrumentation necessary for testing the SERDES IP combined with a strong commitment to ensuring characterization of such IP for extremely high-volume production. The candidate will drive electrical characterization and compliance for cutting-edge SERDES IP that powers Marvell’s flagship products. Responsibilities include ensuring robust performance at 112G/224G Ethernet and PCIe Gen6 speeds, enabling ultra-high bandwidth and low-latency interconnects for tomorrow’s compute platforms.

•    Lead electrical characterization and compliance for SERDES IP targeting Ethernet IEEE 802.3dj and PCIe Gen6 standards.

•    Develop and implement automated validation methodologies, regression frameworks, and compliance test plans for SERDES interface.

•    Drive signal integrity analysis and optimization for high-speed channels, including correlation between modeling, simulation and lab measurements.

•    Provide technical leadership and applications engineering support to strategic customers.

•    Define equipment CAPEX plans for advanced test equipment and ensure readiness for future SERDES IP.

•    Mentor and grow team expertise in high-speed signal integrity and debugging.

•    Represent Marvell in standards committees (IEEE 802.3, PCI-SIG) and influence next-generation interface specifications.

•    Collaborate on high-speed board design, extraction, and characterization, and partner with internal tools teams to build robust test infrastructure.

•    Work closely with executive leadership to define long-term SERDES validation strategies impacting Marvell’s success.

What We're Looking For

•   Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience OR Master’s / PhD degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience. 

•   5-10+ years of direct experience in SERDES characterization and design.

•    Deep expertise in Ethernet IEEE 802.3ck/dj electrical compliance and validation.

•    Strong knowledge of signal integrity principles, channel modeling, and board-level design for high-speed interfaces.
•    In depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer etc.). 

•    Experience in scripting languages development, for example Python, etc.

•    Critical thinking and problem-solving attitude and ownership of the group’s results.

•    Excellent verbal and written communication skills

Expected Base Pay Range (USD)

164,650 - 246,700, $ per annum

The successful candidate’s starting base