Lead Memory Controller Architect/uArch (Principal Engineer)

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a Lead Memory Controller Architect/uArch, you will drive the design and development of advanced memory controller for cutting-edge technologies such as LPDDR5, LPDDR6, PIM (Processing in Memory), and beyond (DDR5, GDDR7, HBM4).

As a key player in this critical position, you will have end-to-end ownership for memory-controller architecture, including microarchitecture, RTL design, and performance/power optimization. You will work closely with cross-functional teams, such as system architects, verification, performance/power, and design implementation, to bring innovative ideas to life and develop cutting-edge memory technologies for Samsung's next-generation products. This role offers a unique opportunity to be at the forefront of the entire technology development cycle, allowing you to expand your expertise in memory controllers and push the boundaries of what is possible, shaping the future of memory technology.

• You possess a strong engineering foundation and extensive experience in architecture, enabling you to lead the development of custom memory controllers, including micro-architecture, RTL design, debugging, and timing closure.
• You have a passion for microarchitecture development, excel at driving the creation of high-quality RTL from initial architectural exploration to final delivery, meeting performance, power, and area (PPA) targets while adhering to project schedules.
• You ensure design excellence, utilizing various tools and methodologies, including LINT, CDC, ECO flows, and power analysis (PowerArtist), to validate design quality and identify areas for improvement.
• You collaborate with cross-functional teams, you foster strong partnerships with stakeholders to guarantee design functionality, achieve PPA objectives, and overcome implementation challenges in a dynamic environment with shifting priorities.
• You take pride in your deliverables, assuming ownership of your work by adhering to JEDEC standards, collaborating with SOC IP delivery teams, performing thorough sanity checks, supporting timing debug and closure, and applying your knowledge of DDR PHY to drive successful outcomes.

Skills and Qualifications

• 20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD
• Proven experience in memory controller micro-architecture and RTL design, owning all sub-blocks of custom memory controller designs.
• Deep expertise in multiple memory technologies, such as LPDDR4/5/6, PIM, DDR, GDDR, and HBM.
• Strong knowledge of JEDEC memory standards and working knowledge of DDR PHY.
• Demonstrated success in driving architecture through RTL design for high-performance digital systems.
• Strong expertise in Verilog and ASIC design flow, including RTL design, verification, synthesis, timing analysis, and ECO.
• Proficiency in scripting languages (Perl, Python) to support design and automation.
• Strong communication and collaboration skills; able to navigate ambiguity in a fast-paced, global team environment.
• Familiarity with interface protocols (AMBA, AXI, ACE) is desired.
• Knowledge of AES, ECC, and RAS features is preferred.
• Self-driven, curious, and passionate about logic design and innovation.

Our Team

Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconduc