Staff Digital Verification Engineer

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Staff Digital Verification Engineer 
Austin, TX 

Meet the Team 

We are focused on producing world-class Wireless MCU products. The architecture specifications, design, verification, emulation, and implementation of the Wireless MCU SoCs are all the responsibilities of our team. The IPs on our chip include an embedded CPU system with analog and digital peripherals, advanced security, advanced power management, and best in class low power wireless modems. We strive to provide advanced technology solutions through innovation in custom RISC-V Cores and AI/ML accelerators.  

The position involves executing a verification plan on digital IP blocks using a combination of simulation and formal verification techniques. The qualified candidate should have built UVM test benches from scratch and taken them through all stages of execution. The candidate will interact with cross-functional teams to receive specs, create, and execute verification plans, and debug IP and system-level issues. Based on the project needs, the candidate will debug chip level tests for functionality, power, and performance.  

Responsibilities 

• Block and IP Verification 

• Create and execute the test plan with emphasis on metrics driven verification  

• Constrained random tests, scoreboard, and coverage development  

• Validate block power and performance requirements 

• Apply formal verification tools like lint, auto, and property checks  

• System Level Verification 

• Debug functional failures at subsystem and SoC levels  

• Perform gate-level verification across corners and provide activity files for power analysis 

• Flows and Methodology 

• Architect and implement Verification Components using UVM-based methods 

• Develop verification flows and methodologies to enhance IP, SoC, and Formal Verification 

Skills You Will Need 

Minimum Qualifications 

• 10+ years of design experience 

• Bachelor's or Master's degree in Electrical/Computer Engineering