Principal ASIC Physical Design Engineer

Company Description

Our Mission

At Palo Alto Networks®, everything starts and ends with our mission:

Being the cybersecurity partner of choice, protecting our digital way of life.

We have the vision of a world where each day is safer and more secure than the one before. These aren’t easy goals to accomplish – but we’re not here for easy, we’re here for better. We are a company built on the foundation of challenging and disrupting, and we’re looking for innovators who are as committed to shaping the future of cybersecurity as we are.

We’re changing the nature of work. Palo Alto Networks is evolving to meet the needs of our employees now and in the future through FLEXWORK, our approach to how we work. From benefits to learning, location to leadership, we’ve rethought and recreated every aspect of the employee experience at Palo Alto Networks.  And because it FLEXes around each individual employee based on their individual choices, employees are empowered to push boundaries and help us all evolve, together.

Job Description

Your Career

As an ASIC Physical Design Engineer, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for performance, reliability, and power efficiency.  You will collaborate closely with our ASIC vendor and lead our ASIC team in floorplanning, closing timing, validating constraints, and optimizing power consumption.  You will define physical design flows and guide the design team on strategies for clocks, resets, and synchronization.  You will collaborate with internal and external stakeholders on defining the electrical specification, chip I/O, and package design.

Your Impact

• Collaborate with hardware engineers to define the electrical specifications, chip I/O, package design, and requirements for power and signal integrity
• Collaborate with external ASIC vendors to define optimal floorplans, power grids, clocking strategies, and custom routing
• Guide internal RTL designers in closing timing, reducing congestion, and optimizing power consumption
• Drive timing closure and constraint validation for the overall ASIC design
• Advise silicon bringup and validation teams on clock, reset, synchronization, and power issues

Qualifications

Your Experience

• BS in EE, CE, or CS required or equivalent military experience required - MSEE preferred
• Minimum 10 years experience in ASIC physical design
• Demonstrated success in taking multiple ASICs from concept to mass production
• Expertise in synthesis and static timing analysis
• Required strengths
  • Guiding floorplanning, chip I/O, and package design
  • Defining and validating complex timing constraints and exceptions
  • Closing timing with static timing analysis and verifying complex clock domain crossing paths
  • Advising senior designers on optimizing congestion and power dissipation
• Preferred experience
  • Physical design for networking ASICs with wide data paths and memory-dominant floorplans
  • Engaging with third-party ASIC vendors in all phases of chip development, including RFQs and SoWs
  • Creating automated flows for top-level integration
  • Installing and managing design and technology libraries
  • Integrating custom IPs including PLLs, serdes, clock dividers, and analog circuits
• Skilled in writing powerful, modular, and scalable programs in Python / Perl / Unix shell to automate physical design and integration tasks
• Demonstrated ownership and independence in planning, managing multiple priorities, driving vendors, and reporting status
• Strong leadership, collaboration, and communication skills

Additional Information

The Team

To stay ahead of the curve, it’s critical to know where the curve is, and how to anticipate the changes we’re facing. For the fastest growing cybersecurity company, the curve is the evolution of cyberattacks, and the products and services that proactively address them. Our engineering team is at the core of our products – connected directly to the mission of preventing cyberattacks. They are constantly innovating – challenging the way we, and the industry, think about cybersecurity. These engineers aren’t shy about creating products to solve problems no one has tackled before. They define the industry, instead of waiting for directions. We need individuals who feel comfortable in ambiguity, excited by the prospect of challenge, and empowered by the unknown risks facing our everyday lives that are only enabled by a secure digital environment.

Our engineering team is provided with an unrivaled opportunity to build the products and practices that will support our company growth over