Principal Memory Controller Micro-Architect/Logic Designer

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a Principal Memory Controller Micro-Architect/Logic Designer, you will contribute to the micro-architecture development and logic design of custom memory controller for LPDDR5, LPDDR6, PIM. This is a principal level role where you will interact with the system architects, verification, performance/power and design implementation teams. You will be own and drive the entire memory controller related RTL design, performance and power optimization, and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success.

• You drive the timely development and debug of new features on timely development of custom memory controller.
• You are familiar with JEDEC standards and timing parameters.
• You have working knowledge of DDR PHY.
• You work on SOC IP delivery with all sanity checks.
• You work on timing debug and closure.
• You work on LINT, CDC flows and analysis.
• You work on power artist flow and power analysis.
• You have experience working on ECO flows.
• You collaborate with the verification team to verify the functionality and correctness of the design.
• You communicate with implementation to achieve your timing and area.
• You produce high quality RTL on schedule meeting PPA goals
• You engage with performance and power team on achieving performance and power goals.
• You partner with the physical design and CAD team to resolve implementation level details.

Skills and Qualifications

• 20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD
• Experience working with memory controller u-architecture.
• Familiarity with different memory technologies like LPDDR4/5/6, PIM, DDR, GDDR, HBM.
• Knowledge of JEDEC memory standards required.
• Working knowledge of DDR PHY.
• Strong background owning and driving the RTL design of all sub-blocks of custom memory controller designs
• Demonstrated experience of successful Architectural through RTL design on high performance digital designs
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis & ECO.
• Understanding of interface protocols such as AMBA, AXI, ACE is desired
• Knowledge of AES, ECC, RAS features preferred.
• Strong communication and interpersonal skills are required, along with the ability to work in a dynamic, global team.
• Experience with a scripting language like Perl or Python.
• Energetic, curiosity, and passion in logic design.

Our Team

Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vast