Staff Engineer, ASIC Design Verification

<div class="content-intro"><p><span style="font-size: 12pt;"><strong>Please Note:</strong></span></p> <p>To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.&nbsp;</p> <p><span style="font-size: 12pt;"><strong>Advancing the World’s Technology Together</strong></span></p> <p>Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.&nbsp;</p> <p>We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.</p></div><p>The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash.&nbsp; DDL’s vision is to solve key problems of Cloud &amp; Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions such as Custom HBM base die, AI accelerators. We are an integral part of Samsung’s strong R&amp;D focus &amp; lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.</p> <p>Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You’ll focus on enhancement of memory and storage capability by developing prototype and production</p> <p>Job: 42935</p> <p>Location: Daily onsite presence in San Jose HQ or Folsom location 5 days week</p> <p><strong>What You’ll Do</strong></p> <ul> <li>Participate in verification strategy and methodology definitions</li> <li>Contribute in micro architecture specification and reviews</li> <li>Responsible for the verification of modules/subsystems of AI accelerators</li> <li>Architect test benches, create test plans, implement test bench components in UVM</li> <li>Execute the verification per plan to the closure</li> <li>Work closely with architects and design engineers to define verification requirements, and to close functional and code coverage targets.</li> <li>Provide support in post silicon bring up and debug</li> </ul> <p><strong>What You Bring</strong></p> <ul> <li>BE (M