Sr. DSP ASIC/FPGA Design Engineer (Silicon Engineering)

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

SR. DSP ASIC/FPGA DESIGN ENGINEER (SILICON ENGINEERING)

Starlink is SpaceX’s ambitious program aimed at bringing broadband connectivity to the globe by building a constellation of thousands of satellites in low earth orbit (LEO). Starlink delivers high-speed, low-latency internet to locations where access has been unreliable, expensive, or completely unavailable. We are developing millions of devices for end users in order to link our customers to our satellites. As a member of our Silicon Engineering group, you will have the unique opportunity to design digital communication blocks for complex silicon products that are at the heart of the Starlink network. In this critical role, as a DSP ASIC/FPGA Design Engineer, you will be collaborating with silicon, antenna, software, and other engineering teams to deliver cutting-edge solutions that will take Starlink to the next level.

RESPONSIBILITIES:

• Participate in all phases of ASIC/FPGA design flow - from concept to mass production
• Develop high-level design requirements and block-level micro-architectures, partition design within ASIC/FPGA, and create specification documents
• Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer, error correction, etc.)
• Optimize your designs for area, speed, and power to meet system requirements; analyze architectural trade-offs
• Develop test benches and test cases for block-level functional verification, emphasizing bit-matching and self-checking
• Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers
• Collaborate with verification engineers to develop UVM-based top-level tests for your blocks
• Participate in SoC-level and FPGA top-level integration activities
• Prototype designs on FPGA, focusing on closely emulating the final product functionality
• Use scripting languages to achieve higher performance and improve productivity through automation
• Perform lint checking, CDC checking, logic equivalence checking, and other EDA tool-based checks
• Run implementation tools, such as Synopsys Design Compiler, Xilinx Vivado, and others; perform timing closure for your designs
• Work with backend/implementation teams to address synthesis, timing, layout, and DFT issues for ASICs
• Bring-up and validate ASICs and FPGAs in the lab, utilize various lab equipment
• Collaborate with software engineers in developing production software for your designs

BASIC QUALIFICATIONS:

• Master's degree in an engineering discipline
• 5+ years of experience in SystemVerilog, Verilog or VHDL RTL design
• Experience designing DSP and/or digital communication system datapath blocks

PREFERRED SKILLS AND EXPERIENCE:

• Experience in working with ASICs and/or FPGAs
• Experience in designing DSP, digital communication system datapath blocks, and/or modem design
• Strong programming and scripting skills in most of these languages: MATLAB, Python, C/C++, Perl, Tcl, Make, Bash
• Understanding of clock domain crossing (CDC) techniques
• Experience in FPGAs, evaluation boards, and knowledge of FPGA design flow
• Understanding of different DSP architectures and tradeoffs (including transforms, filtering, sample rate conversion, etc.)
• Knowledge of different digital modulation techniques (e.g. PSK, QAM, OFDMA, etc.)
• Knowledge of wireless communications systems and standards (e.g. LTE, Wi-Fi, Bluetooth, etc.)
• Knowledge of forward error correction (FEC) blocks, such as LDPC, Turbo Codes, convolutional/Viterbi, and Reed-Solomon codecs
• Knowledge of industry standard interfaces, protocols, and architectures: PCIe, Ethernet, AMBA, DDR, etc.
• Experience in developing automated, self-checking test benches and/or UVM
• Experience in EDA tools such as simulators (e.g. Questa), lint checkers (e.g. Spyglass), synthesis (e.g. Design Compiler), FPGA tools (e.g. Vivado)
• Experience in formal verification and logic equivalence checking, knowledge of LEC tools (e.g. Formality)
• Knowledge of power optimization, power estimation, UPF-based power verification
• Experience in Git version control system
• Knowledge of synthesis and static timing analysis, knowledge of timing closure techniques for high-speed designs, knowledge of STA tools (e.g. PrimeTime)
• Experience in Atlassian collaboration