Sr Principal ASIC Design Engineer (NetSec)

Company Description

Our Mission

At Palo Alto Networks® everything starts and ends with our mission:

Being the cybersecurity partner of choice, protecting our digital way of life.
Our vision is a world where each day is safer and more secure than the one before. We are a company built on the foundation of challenging and disrupting the way things are done, and we’re looking for innovators who are as committed to shaping the future of cybersecurity as we are.

Who We Are

We take our mission of protecting the digital way of life seriously. We are relentless in protecting our customers and we believe that the unique ideas of every member of our team contributes to our collective success. Our values were crowdsourced by employees and are brought to life through each of us everyday - from disruptive innovation and collaboration, to execution. From showing up for each other with integrity to creating an environment where we all feel included.

As a member of our team, you will be shaping the future of cybersecurity. We work fast, value ongoing learning, and we respect each employee as a unique individual. Knowing we all have different needs, our development and personal wellbeing programs are designed to give you choice in how you are supported. This includes our FLEXBenefits wellbeing spending account with over 1,000 eligible items selected by employees, our mental and financial health resources, and our personalized learning opportunities - just to name a few!

At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is why our employees generally work full time from our office with flexibility offered where needed. This setup fosters casual conversations, problem-solving, and trusted relationships. Our goal is to create an environment where we all win with precision.

Job Description

Your Career

Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer, you will take end-to-end ownership of complex modules or subsystems from architectural definition through silicon bring-up. You will provide technical leadership, collaborate extensively with world-class verification and physical design engineers to hit aggressive performance, power, and schedule goals, and mentor less experienced team members. This role requires a deep technical background in ASIC design for networking applications and the ability to independently drive major design efforts.

Your Impact

• Define and document clear, comprehensive design and micro-architecture specifications for complex digital logic blocks and subsystems.

• Design high-quality, high-performance SystemVerilog RTL that meets aggressive area, performance, and power targets, with particular emphasis on complex datapath designs.

• Lead debug efforts across simulation, emulation, formal methods, and silicon bring-up environments.

• Partner closely with verification engineers to define test plans, debug complex scenarios, close coverage, and add design-for-debug features.

• Collaborate effectively with physical design teams, including reviewing synthesis/timing reports, rewriting RTL to close critical paths, analyzing timing, power, and area reports, and consulting on floor-planning for congestion/routability. Drive timing closure from an RTL perspective, understanding core concepts like setup/hold constraints and delay sources.

• Mentor junior and senior staff engineers, providing technical guidance and fostering their growth in ASIC design best practices, particularly in areas like design methodology and problem-solving approach.

Qualifications

Your Experience

Required Qualifications

• BS in EE, CE, or CS (MSEE or equivalent military experience preferred).

• 15+ years of hands-on front-end ASIC design experience, with significant ownership of multiple complex modules or subsystems from specification through mass production silicon.

• Expert-level proficiency in SystemVerilog RTL design.

• Deep and demonstrable strength in digital logic design fundamentals, including state machines, synchronous and asynchronous FIFO design, flow control mechanisms (e.g., ready/valid, credits, backpressure), and the understanding and avoidance of head-of-line blocking and deadlock situations in complex datapaths.

• Expertise in defining micro-architecture from high-level requirements for large and intricate digital blocks.

• Advanced debugging skills across various verification platforms and silicon.

• Strong command of