Senior Staff ASIC Design Engineer

General Information

Job Title Senior Staff ASIC Design Engineer Job ID 9793 City Hillsboro State/Province Oregon Date Posted 26-Feb-2025 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote Eligible No Base Salary Range: $135000 - $203000

Descriptions & Requirements

Job Description and Requirements

We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
As a Verification Design Engineer, you are passionate about ensuring the highest quality in analog and mixed-signal designs. You possess a keen eye for detail and are driven by a desire to solve complex problems. Your background in testplan review and PHY verification strategy makes you an ideal candidate for this role. You thrive in collaborative environments and are eager to coach and enable teams to achieve their best. With your strong technical foundation in firmware and PHY quality, you are ready to make a significant impact at Synopsys.
What You’ll Be Doing:
Collaborating with cross-functional and cross-geo teams to define and implement best in class Die to Die IP design at PHY and controller levels.Develop and implement PHY verification strategies and comprehensive test plans.Review and refine test plans to ensure alignment with project goals and industry standards.Implement PHY and controller testbenches, monitors and scoreboards using UVM methodology Achieve code coverage goals and ensure thoroughly verified designs Work with the Lab/System team for test plan, silicon bring up and debugConduct Analog Mixed Signal Verification and Validation (VAL) for high-quality Die to Die IPCollaborate with firmware teams to integrate and test firmware components.Ensure the highest standards of Die to Die PHY quality through rigorous testing and validation processes.Coach and enable the global Verification and Validation (VN) team to achieve optimal performance.