Manager/Director of Hardware Engineering

<div class="content-intro"><p><strong>Baya Systems is inspired by the&nbsp;<a href="https://bayasystems.com/about/">baya bird</a>, also known as the&nbsp;<a href="https://bayasystems.com/about/">weaver</a>. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.</strong></p> <p>Baya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. &nbsp;We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!</p></div><p></p> <p><span data-teams="true">Manager/Director of Hardware Engineering</span></p> <p><span data-teams="true">Santa Clara, CA (</span><span data-teams="true">Onsite only)</span></p> <p><span data-teams="true">Reports to: VP of Hardware Engineering</span></p> <p>&nbsp;</p> <p><strong>Role Overview</strong></p> <p>As a Hardware Engineering Manager, you will lead a talented, first-level team of RTL Microarchitects and Design Verification (DV) Engineers. Operating in a fast-paced IP interconnect startup environment, you will own the end-to-end execution of high-speed interconnect IP blocks. You will ensure first-pass silicon success by driving microarchitecture, RTL design, and rigorous verification methodologies.</p> <p><strong>What You’ll Do</strong></p> <ul> <li><strong>Team Leadership:</strong> Directly manage, mentor, and grow a team of 8-12 RTL and DV engineers.</li> <li><strong>Execution &amp; Delivery:</strong> Drive the development of high-speed interconnect IP from microarchitecture specifications to RTL implementation and tape-out.</li> <li><strong>Verification Excellence:</strong> Oversee the development of robust, coverage-driven verification test plans, UVM/OVM environments, and emulation platforms.</li> <li><strong>Cross-Functional Collaboration:</strong> Work closely with architecture, physical design, and system team