Senior Firmware Engineer - PCIe/CXL Memory Solutions

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p>Astera Labs is seeking experienced <strong>Senior</strong> <strong>Firmware Engineer PCIe/CXL Memory Solution </strong>to lead the design and development of embedded firmware for cutting-edge <strong>PCIe/CXL memory expansion products</strong> tailored for AI and Cloud infrastructure. This role is pivotal in enabling next-generation memory devices that power high-performance computing platforms. This position will be required onsite.</p> <p><strong>Required Experience:</strong></p> <ul> <li>Bachelor’s degree in Electrical Engineering, Computer Science, or a related technical field.</li> <li>5+ years of hands-on experience in embedded firmware development using C.</li> <li>Deep expertise in low-level firmware for hardware bring-up, traffic enablement, and RAS (Reliability, Availability, Serviceability) feature implementation.</li> <li>Proven track record working with high-speed interfaces and protocols such as PCIe, CXL, DDR, and I2C.</li> <li>Hands on experience in CPU to Device, Device to Device flows like MMIO, DMA, PCIe P2P.</li> </ul> <p><strong>Key Responsibilities &amp; Skills:</strong></p> <ul> <li>Firmware development, bring-up, and validation of PCIe/CXL/DDR interfaces at PHY and Link layers.</li> <li>Interpret technical specifications and develop robust, low-level C code in RTOS environments.</li> <li>Collaborate effectively with cross-functional teams and external partners to deliver weekly firmware releases and feature demonstrations.<