Staff Software Engineer — SubSystem Integration Test (SSIT)

As part of the AISW engineering team at Qualcomm, you will be the software system integration test (SSIT) engineer for the Delegates portfolio — ONNX Runtime (QNN Execution Provider), ExecuTorch (HTP/QNN backend), and TFLite / LiteRT.  You will own subsystem-level validation at the feature development stage — working side-by-side with software engineers to define test strategy early, build targeted test content, and ensure each feature is solid before it transitions to QA and System Integration Test (SIT). This is a shift-left quality role: you are a co-owner of feature quality from inception, not a downstream gatekeeper.

As part of the AISW engineering team at Qualcomm, you will be the software system integration test (SSIT) engineer for the Delegates portfolio — ONNX Runtime (QNN Execution Provider), ExecuTorch (HTP/QNN backend), and TFLite / LiteRT.  You will own subsystem-level validation at the feature development stage — working side-by-side with software engineers to define test strategy early, build targeted test content, and ensure each feature is solid before it transitions to QA and System Integration Test (SIT). This is a shift-left quality role: you are a co-owner of feature quality from inception, not a downstream gatekeeper.

What You'll Do

Feature-Level Test Strategy & Planning

• Partner with delegate engineers from feature inception to define testability requirements, acceptance criteria, and subsystem test plans covering ORT QNN-EP, ExecuTorch HTP backend, and LiteRT delegate

• Own SSIT test strategy per feature: scope, entry/exit criteria, coverage targets, and risk-based prioritization — aligned with the development team before implementation begins

• Embed in sprint planning, design reviews, and code reviews to ensure features are architected for testability from day one

Test Content Development & Execution

• Develop and maintain automated test content targeting the subsystem boundary: op and feature coverage, numerical accuracy, model-level functional correctness, and backend interface contracts

• Validate on-device behavior on Snapdragon SoCs using HIL infrastructure, covering functional correctness, latency, and memory under real hardware conditions

• Build Python/PyTest-based test suites integrated into the Delegates CI pipeline; ensure SSIT gates are enforced on every code change

• Develop and leverage AI-assisted tooling and agentic workflows (Claude Code, GitHub Copilot) to accelerate test content generation, coverage analysis, and failure triage

Defect Triage & Root Cause Analysis

• Triage failures and isolate root causes across the delegate stack — ML framework → QNN runtime → HTP hardware — and drive resolution with development owners

• Flag integration risks early during feature development; distinguish subsystem-level issues from upstream framework bugs and downstream backend or system integration issues

QA & SIT Handoff

• Define and own handoff criteria from SSIT to QA and SIT: documented test results, known issues, coverage gaps, and risk summaries that give downstream teams a clear picture of feature readiness

• Serve as the primary technical liaison between the Delegates development team and QA/SIT — translating feature context into actionable test guidance for downstream teams

• Maintain traceability between SSIT artifacts and QA/SIT test plans via JIRA; feed defects found in QA/SIT that trace to subsystem gaps back into SSIT coverage

Preferred Qualifications: