Physical Design Engineering, VP

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><span data-contrast="auto">Astera Labs is seeking a VP<strong>&nbsp;of Physical Design </strong>to lead our critical full-chip physical design efforts for next-generation switching products featuring UCIe and&nbsp;UALink&nbsp;technologies. This strategic leadership role will drive the physical implementation of&nbsp;highly complex, multi-die&nbsp;chiplet&nbsp;architectures that are essential to enabling rack-scale AI infrastructure. As AVP, you will scale and mentor a growing team of physical design engineers while&nbsp;establishing&nbsp;the methodologies and flows&nbsp;required&nbsp;to deliver multiple high-performance&nbsp;tapeouts&nbsp;in advanced process nodes.</span><span data-ccp-props="{&quot;134233279&quot;:true}">&nbsp;</span></p> <p><span data-contrast="auto">This role sits at the intersection of&nbsp;cutting-edge&nbsp;connectivity technology and semiconductor execution excellence. You will partner closely with architecture, digital design, packaging, and silicon engineering teams to ensure our switching solutions meet the aggressive performance, power, and area targets demanded by hyperscale AI data centers. Your&nbsp;expertise&nbsp;in interposer design, die-to-die interfaces, advanced packaging, and timing closure will be critical as Astera Labs continues to push the boundaries of AI connectivity with PCIe Gen 6/7 and&nbsp;UALink&nbsp;technologies.</span><span data-ccp-props="{&quot;134233279&quot;:true}">&nbsp;</span></p> &l