Physical Design/CAD Engineer

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p>As an Astera Labs <strong>Physical Design/CAD Engineer</strong> you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff.&nbsp;This role is fully on-site and in-person.</p> <p><strong>Key Responsibilities</strong></p> <ul> <li>As Physical Design CAD Engineer you will support and build flows for world class EDA tools.</li> <li>Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems.</li> <li>Architect and recommend flow improvements and enhance existing methodology for high performance design.</li> <li>Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc.</li> <li>Work with cross function teams to define requirements and specifications to achieve best PPA</li> <li>Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity</li> <li>Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.</li> </ul> <p><strong>Basic Qualifications</strong></p> <ul>