Senior Member of Technical Staff Ref #91403

Responsible for finding and capturing the representative memory and bus transaction traces fromthe target applications, modeling the memory subsystem performance features, simulating thetransaction traces through the performance model, analyzing the performance results, and comingup with ideas to improve the performance and reduce power and design complexity. Integrateperformance models from various IP blocks in the SOC. Model the architecture performancefeatures from reading and understanding the published research papers of the architecture featuresand algorithms. The areas include memory controller, DDR memory interface, IO interface,prefetches, caching, interconnects, data coherency, and memory management. Verify resultsagainst the published data and perform competitor analysis. Perform the modeling of the SOCfabric and memory subsystem features in C or C++ for assessing the features’ impact on theperformance, design feasibility, and power. Correlate the results between the performance modelsand RTL models to make sure the RTL implementation performs close to the performanceprojection. Debug the performance model as well as RTL model to root cause the reasons for thedifferences. Work with the RTL designers and other performance architects on fixing bugs orchanging how the features are modeled. Work with the designers and architects on assessing theperformance impacts from various components in the SOC and suggesting ideas to improve theoverall performance.

Education

• Master’s or foreign equivalent in Computer Science or related field

Experience

• 3 years of experience in job offered or related occupation.

Special Requirements: Must have at least 1 year of prior work experience in each of the following:

1. Developing and implementing SOC (system on chip) C model and interface it to the different agent.2. Conducting experiments and tests to run trade-off analysis for different design choices.3. Validating RTL performance and correlate the C model against RTL.4. Tune design parameters to satisfy performance requirements and for performance optimization.**Telecommuting allowed for this position**Worksite: 3315 Scott Blvd, Santa Clara, CA 95054Applicant Instructions: Include job code 91403 in application. EOE