Director, ASIC Verification

Director, ASIC Verification

  

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description:

   

Strong focus on advanced silicon and system-level verification. Work consists of designing, developing, analyzing, troubleshooting, and debugging complex ASIC and SoC verification environments, system models, and methodologies. Supports development of products, services, and solutions within HPE’s networking portfolio. Requires deep expertise in hardware verification engineering disciplines, methodologies, and tools—including SystemVerilog, UVM, SystemC modeling, and hardware emulation platforms.

Directs and manages a diverse team of senior verification engineers and architects responsible for ASIC/SoC verification strategy, methodology, planning, and execution. Responsible for setting the technical direction for functional verification, modeling frameworks, and emulation acceleration strategies across the organization. Ensures alignment of verification strategy with product architecture and functional goals.

Responsibilities

• Provides direct and ongoing strategic leadership for a verification team consisting of multiple managers and senior technical leaders focused on ASIC/SoC verification using SystemVerilog, UVM, SystemC modeling, and emulation platforms.
• Drives creation and deployment of scalable, reusable verification architecture, methodologies, and infrastructure for complex ASIC programs.
• Creates strategic and tactical resource plans, verification roadmaps, milestones, and priorities for assigned teams based on product architecture, schedules, and technology needs.
• Ensures high-quality, comprehensive verification coverage—including functional, power, performance, and system-level validation.
• Defines and oversees SystemC/TLM modeling strategy to enable early firmware development; ensures tight coupling between virtual models and RTL verification environments.
• Leads emulation and acceleration initiatives to improve verification throughput and software validation readiness; partners with pre-silicon firmware and validation teams.
• Manages headcount, schedules, costs, and deliverables while driving continuous improvement in verification efficiency, automation, coverage closure, and reuse.
• Collaborates closely with architects, RTL design leads, program management, validation, and system engineering to communicate verification status, escalate issues, and drive cross-functional decisions.
• Manages relationships with EDA vendors, emulation platform providers, and global development partners  
• Identifies opportunities for verification flow innovation, methodology improvements, and productivity enhancements.
• Provides overall people-care management including hiring, talent development, performance planning, coaching, and organizational skill evolution.

Education and Experience Required

• First-level university degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience required; advanced degree preferred.
• Typically 15+ years of ASIC/SoC design and verification experience, including:
  • 10+ years of people management, leading large verification or silicon teams.
  • Proven experience directing complex verification programs at scale.
• Deep hands-on expertise in SystemVerilog, UVM methodology, and SystemC/TLM modeling.
• Experience with hardware emulation platforms (e.g., Palladium, Veloce, ZeBu) strongly preferred.
• Networking experience is desirable.

Knowledge and Skills

• Strong leadership capabilities with demonstrated ability to lead senior technical talent and large engineering organizations.
• Expert knowledge of ASIC/SoC verification methodologies, coverage-driven verification, constrained random testing, testbench architecture, and modeling.
• Strong understanding of silicon development flows from architecture to tape-out and post-silicon bring-up.
• Proven experience with em