Sr. ESD Design Engineer

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves diverse high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our diverse and innovative team is helping connect, protect and power our planet.

 

Synopsis

Qorvo is seeking a diversely experienced design engineer to support ESD design engineering for CMOS and SOI technologies, ESD test site, ESD library qualification, and design verification. Applicant should have sufficient design experience to be able to effectively review designs and communicate ESD design deficiencies to product design engineering. 

 

Responsibilities

• Research, development, and characterization of ESD protection cells for both HBM and CDM protection of silicon-based technologies.
• Review designs for ESD protection design robustness. Provide advice and guidance in proper implementation of the ESD protection cells in RF and analog applications.
• Continue the development of “best practices” for ESD in the technologies that are being supported.
• Characterize ESD circuits using TLP, VF-TLP, and other electronic characterization methods.  Provide characterization information to design engineering on devices that need characterization.
• Design enablement of ESD and I/O cells with the part functionality.  This will include understanding ESD protection design, latch-up, transient latch-up as well as ESD design verification and EDA tools.
• Provide support and expertise for implementation of device testing test plans (HBM and CDM). This includes understanding the tests sufficiently so as to define the test pin combinations for tests.
• Provide co-design support with both ESD and RF simulations of circuits to maximize both performance and ESD protection robustness.
• Interface with customers, both internal and external, in the event of ESD and EOS (EIPD) failures and resolution plans.

 

Job Requirements

1. In-depth knowledge and experience with ESD design for RF, analog, digital and mixed-signal IC designs.
2. An extensive understanding of semiconductor physics as it relates to electrical overstresses.
3. Tool experience to include circuit design and layout using the ADS and/or Cadence suite of design tools (p-cell based layout, Mentor-Graphics DRC/LVS, connectivity checking, and parasitic wiring extraction).
4. Proficiency with the ESRA tool (Synopsis) and coding for ESD design reviews.
5. An in-depth knowledge of the device testing Standards (ANSI/ESDA/JEDEC JS-001 and JS-002).
6. The successful candidate should have very well developed written documentation and verbal communication skills. A willingness to broadly engage designers and technologists is required.
7. Demonstrated leadership experience in a diversely complex cross disciplinary environment is required.

 

Education

MSEE or Ph.D. Electrical Engineering preferred.

 

Experience

2+ years of diverse design experience wit