Principal Engineer - Low Power Chip Architect / System Engineer

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

We are seeking a senior-level Low Power Chip Architect / System Engineer with deep expertise in mixed-signal IC and system design and a proven record of chip-level technical leadership. This is a high-impact role responsible for defining the architecture, driving transistor-level design, and enabling system-level integration of ultra-low-power integrated circuits (ICs) for Robotics and Industrial IoT (IIoT) applications.

The successful candidate will bridge high-performance Analog Front Ends (AFEs) with digital logic and firmware, leading programs from initial architecture and specification through simulation, verification, tape-out, and early silicon bring-up. This role requires strong cross-functional collaboration, sound architectural judgment, and the ability to operate effectively in ambiguous environments.

** Position requires to be onsite in San Diego, 5 days a week. **

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

Responsibilities:

Architecture & Technical Leadership

• Define and support end-to-end system architecture, including partitioning across analog, digital, firmware, and system domains
• Drive architectural trade-offs across power, performance, noise, latency, and silicon area
• Partner with chip leads and system leads from concept definition through silicon bring-up and validation

Mixed-Signal Design & Integration

• Lead feasibility studies and transistor-level design of mixed-signal building blocks including ADCs, DACs, PLLs/DLLs, LDOs, and SerDes
• Architect and integrate ultra-low-power AFEs optimized for battery-operated IIoT and Robotics sensor ASICs
• Drive full-chip execution in collaboration with internal teams and third-party IP vendors and design houses

Modeling, Verification & Silicon Execution

• Develop behavioral and system-level models using MATLAB/Simulink (or equivalent tools) to evaluate noise, linearity, and SNR
• Perform comprehensive pre-silicon verification across PVT corners using industry-standard simulators
• Support post-silicon bring-up, characterization, and reliability qualification, including HTOL and burn-in
• Collaborate with packaging, test, and system teams to ensure successful productization

System & Application Enablement

• Support multi-modal sensor data acquisition, sensor fusion, and edge AI inference workflows
• Contribute to hardware–software integration for efficient system-level deployment

Preferred Qualifications:

• Ph.D. in Electrical Engineering (or related field) with 8+ years of post-degree industrial IC/system design experience OR
• M.S. in Electrical Engineering (or related field) with 10–12+ years of industrial IC/system design experience
• Strong expertise in low-power analog and mixed-signal (AMS) IC design
• Hands-on experience with Cadence Virtuoso, AMS sims, verilog and related analog design tools
• Proficiency with Spectre, HSPICE, and board-level simulation methodologies
• Solid understanding of PDKs, LVS, DRC, and PEX flows
• Proven experience with ESD and reliability standards (HBM, CDM, TLP)
• Advanced academic background in Electrical Engineering or a closely related field
• Extensive industry experience in mixed-signal IC and system-level design
• Demonstrated experience as a Chip Lead, System Architect, or Technical Lead
• Proven ability to drive end-to-end silicon programs from concept to production
• Strong capability to work independently and provide technical direction with minimal supervision
• Experience with digital design flows, including synthesis and timing analysis
• Familiarity with firmware development and software integration
• Working