Jobs and Careers

ASICS Design Verification Engineer

qualcomm

San Diego, United Statesfull_timeVerifiedPosted 23 Jun 2026

💰 $173,400/yr($115,600/yr – $173,400/yr)

About the role

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The responsibility of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Involve in developing automation to improve verification efficiency.

Qualifications

Bachelor's degree in Engineering, Science, or a closely related field
2+ years of experience with ASIC design and verification tools, techniques, and methodology

Preferred Qualifications

Master’s degree in Computer Science, Electrical Engineer, Computer Engineering, or a closely related field
6+ years of experience with ASIC design and verification tools, techniques, and methodology
6+ years of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL.
6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills.
6+ years of experience with developing block-level testbench environment using SystemVerilog
6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification
6+ years of experience with scripting/automation skills using either Perl or python
Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable (not mandatory)
Knowledge or experience with Assertion Based Formal Verification is desirable (not mandatory)

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

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