Senior Digital Design Engineer

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

About Analog Devices (ADI) 

Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure, and connect. 

The Position 

Analog Devices is seeking a senior digital design engineer for its Data Center & Energy (DCE) group in beachside Santa Barbara, CA. Within DCE, we deliver high‑reliability power, connectivity, and analytics solutions for modern data centers and energy infrastructure. 

The successful candidate will implement and verify digital logic for mixed-signal SoCs that enable signal measurement and analytics. This role focuses on RTL development, verification, and integration, working closely with senior engineers and cross-functional teams to deliver robust, manufacturable solutions. 

This is a demanding multi-disciplinary position with unique growth potential. The group culture aims to foster a challenging, exciting, and supportive environment. The team members must be comfortable working on a wide variety of products and technologies in a fast-paced and agile environment. Analog Devices rewards performance, innovation, and collaboration. 

Responsibilities include, but are not limited to: 

• Develop and verify RTL for digital blocks and subsystems; ensure functional correctness and timing closure 

• Perform synthesis, static timing analysis, and support design-for-test (DFT) insertion and pattern generation 

• Collaborate with analog, firmware, and validation teams to integrate digital content into mixed-signal SoCs 

• Assist with silicon bring-up and debug; support lab measurements and correlation to simulation 

• Contribute to methodology improvements and automation initiatives 

Minimum Qualifications: 

• BS in Electrical or Computer Engineering (or equivalent) 

• 3+ years of experience in ASIC/SoC digital design 

• Proficiency in Verilog/SystemVerilog and scripting languages (Python, C) 

• Familiarity with RTL-to-GDS flows (e.g., Genus, Innovus, Tempus, Confor