Senior Process Integration Engineer

CA Pay Range (Annual):

$112,000.00 - $208,000.00

At Infinera, your base pay is one part of your total compensation package. Your actual base pay will depend on your skills, qualifications, experience, and location. This role may be eligible for equity grants, discretionary bonuses, or commission payments. The amount of these incentives is based on the terms of the Company’s incentive plans, the Company’s financial performance, and/or individual employee job performance.

Infinera also offers paid leave, medical, 

dental, and vision coverage, 401(k),

life, and disability insurance to eligible employees.

Title: Senior Process Integration Engineer,

Location: Sunnyvale, CA / San Jose, CA

As Senior Process Integration Engineer, you will ensure high quality and reliability of InP-based Photonic Integrated Circuit (PIC) products through extensive experiments and data analysis.  You will have the opportunity to help bring up our new high volume fab in San Jose, CA. You will work with various functional teams to troubleshoot and improve wafer fabrication processes, develop qualification plans for wafer-level process improvements, maintain design files for process test structures, and drive improvements in yield reliability

Your Key Responsibilities Would Include:

• Manage quality and yield of PIC wafers based on knowledge of fab processes, device physics, and the analysis of test and reliability data
• Troubleshoot and resolve process deviations and test failures through a detailed analysis of test data and process history
• Establish and maintain inline FAB process specifications.
• Continuous surveillance of inline FAB process capability (CPK)
• Investigate the impact of design rules on process yields, develop test structures for effective process control
• Initiate and carry out yield improvement activities, from inception through qualification and implementation
• Support next-generation PIC platform development and participate in technology development, transfer, and ramp activities to meet yield, reliability, cost, and device performance goals
• Support Process Engineering to improve process stability and capability
• Support Operations to improve throughput and cycle time

Education & Experience Necessary For Success:

• Understanding of semiconductor processes and device physics
• Semiconductor FAB / cleanroom environment experience
• Understanding of statistical process control methods
• Familiarity with or direct experience in most of the standard III-V process technologies required for wafer fabrication such as epitaxy, wet etching, plasma etching, metal deposition, and photolithography
• Ability to work in a CAD design environment, generate and maintain mask files as well as die level test structure files
• Database interrogation, statistical analysis skills, and design of experiments
• Excellent communications skills and ability to present data, ideas, and recommendations to a diverse audience

Education Required:

B.S. with at least 3 years of work experience.  M.S. level or higher in Electrical Engineering, Photonics, Physics, or Materials Science is preferred.

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“This position requires direct or indirect access to certain confidential information, hardware, software, technology, or technical information (referred to here as “Export-Controlled Information”) controlled under the U.S. International Traffic in Arms Regulations (ITAR) and/or the U.S. Export Administration Regulations (EAR). All personnel in this position must be eligible to or be able to obtain authorization from the appropriate agency to access applicable Export-Controlled Information. The U.S. Department of Commerce currently requires a foreign person with a most recent citizenship or permanent residency of Sudan, Ukraine, or a country currently designated in Country Group D:1, E:1 or E:2 (Supplement No.