Advanced Package Development Engineer

About Eridu AI 

Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today’s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI’s solution and value proposition have been widely validated with several hyperscalers.  

The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World’s leading micro-LED display company and developer of the first augmented reality contact lens).

Position Overview

We are seeking an Advanced Packaging Engineer with expertise in advanced packaging technologies, including 2.5D CoWoS, bridge-based multi-die assembly, and high-density chiplet integration. This individual will drive the development, integration, qualification, and production ramp of advanced IC packaging solutions for high-performance, next-generation semiconductor products.

This role requires hands-on experience with advanced packaging development, fine-pitch interconnect, substrate and interposer technologies, and multi-die/package co-design. The successful candidate will interface closely with foundries, OSATs, substrate vendors, and system engineering teams to drive process optimization, and volume production.

Responsibilities 

• Leading and execution of evaluation of materials, processes, and design rules for multi-die packaging (e.g., chiplets on interposer or bridge-based platforms).
• Drive package integration flows, including die attach, microbump bonding, assembly, underfill, molding, and substrate attach processes.
• Partner with foundry and OSAT vendors to oversee engineering builds, tooling readiness, material availability, and risk mitigation strategies during development.
• Lead early learning, risk mitigation, and qualification activities for multi-die integration using 2.5D interposer.
• Evaluate and implement design-for-manufacturing (DFM), design-for-yield (DFY), and design-for-reliability (DFR) best practices into packaging flow.
• Support root cause analysis and corrective actions for process or yield-related issues, including material or assembly-related excursions.
• Lead coordination of package process improvements, early learning activities, and qualification milestones for multi-die chiplet integration using 2.5D CoWoS, and MCM packaging assembly methods.
• Guide thermal, mechanical, and electrical tradeoff assessments during early-stage package design and development.
• Contribute to the definition of material specifications, integration process flows, and best practices for scalable package development.
• Interface with cross-functional teams to ensure packaging solutions meet technical requirements, BOM, and program schedules.
• Support root cause analysis and corrective action processes for build issues, resolve quality excursions, and material-related challenges.
• Ensure packaging solutions meet DFM, thermal, mechanical, and reliability targets at both the component and system levels.
• Contribute to the development of material specifications, process flows, and integration guidelines based on test vehicle results and partner feedback.
• Deliver regular technical updates, risk assessments, and milestone reports to internal and external stakeholders.

Qualifications

• Bachelor’s degree in Mechanical, Electrical, Chemical Engineering, or a related field.
• 8+ years of hands-on experience in advanced IC packaging and multi-die integration, including 2.5D CoWoS or bridge-based assembly.
• Proven track record developing and qualifying package technology’s enablement and process optimization and validation.
• Understanding of substrate t