Senior Technical Staff Engineer - Design (IO Lead Design-FPGA)

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Job Description:

Microchip Technology Inc. has a Senior Technical Staff Engineer - IO Design Lead opening based in Chandler, Arizona. This engineer will be responsible for providing technical leadership in the architecture definition, design, modeling, integration, and verification of complex analog circuitry (clocking, Rx, Tx) integrated into the IO’s of the FPGA.

• Develop analog circuits for GPIO, HSIO, high-speed DDR and other IO applications in advanced FinFET nodes.

• Work with architecture team to understand chip requirements and translate them into circuit architectures and implement and simulate them.

• Contribute to the micro architecture and circuit design, simulation and optimization of various IO blocks such as clocking (PI, DLL, PLL), CTLE, VGA, Tx.

• Collaborate with layout and ASIC PnR team to optimize IO floorplan, placement and routing of power and critical signals.

• Develop IO system models to determine system budgets, identify performance bottlenecks and create implementable design specs.

• Drive analog and digital design, AMS verification, layout across different geographies and time zones.

• Improve current and develop new calibration and training algorithms of various sub-blocks in the IO’s to meet high-speed performance.

• Work with the ESD engineer to integrate the ESD design into IO blocks.

• Layout guidance and mentorship of junior engineers.

• Work with the layout lead in planning the distribution of critical signals and clocks, placement of IO blocks, and design of the IO power distribution network.

• Propose new mixed-signal flows for IO designs that will enhance the efficiency and quality of current and future designs

• Investigate new architectures and circuit design techniques for current and future generations of FPGA IO’s.

• Support IO Mixed-Signal IP through post-tapeout phase, including lab testing, customer bring-up and debug.

Requirements/Qualifications:

• Bachelors and/or Master’s in Electrical Engineering, Physics, Computer Engineering or Computer Science preferred.

• 15+ years of proven silicon experience in design and verification of high-speed IOs and verification efforts in multiple technology nodes.

• System modeling of IO’s using Matlab and System C/System Verilog.

• Familiarity with FinFet technology. Knowledge go industry standard tools like Spice, Virtuoso, AMS/Co-sim, Matlab.

• Competency in HSPICE, co-sim, and testbench generation and simulation.

• Knowledge about high speed design techniques (DDRx, PCI-e, USB, MIPI) and calibrations.

• Demonstrated competency in scripting, managing simulation queues, and data capture