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Senior RTL Design Engineer

Capgemini
United Statesfull_timeVerifiedPosted 12 Jul 2025

About the role

Senior RTL Design Engineer-080636

Description

 

About the Job You’re Considering

As a RTL Logic Design Engineer, you’ll be at the heart of innovation—designing and implementing high-performance digital systems that integrate seamlessly with mixed-signal IP.

Your Role:

  • Crafting microarchitecture and implementing block-level logic using System Verilog
  • Integrating digital designs with mixed-signal IP for block-level simulation
  • Writing high-quality RTL code with embedded assertions and coverage points
  • Performing design clean-up using LINT, CDC, and RDC checks
  • Collaborating with the Verification team to prepare test plans, debug designs, and enhance code coverage
  • Developing and analyzing functional coverage metrics
  • Debugging behavioral RTL issues in Mixed-Signal IP
  • Partnering with the Physical Design team to resolve timing closure challenges

Required Skills:

We’re looking for someone who brings both experience and leadership to the table:

  • Bachelor’s Degree in Electrical or Computer Engineering or a related field
  • 10+ years of hands-on experience in Logic (RTL) Design
  • Strong technical leadership with the ability to guide cross-functional teams on SoC execution
  • Deep understanding of SoC architecture and the ability to translate architectural specs into implementation details
  • Proven experience in PCIe and Ethernet IP integration
  • Proficiency in AMBA-based bus protocols (CHI, AXI, AHB, APB)
  • Excellent communication skills—clear, collaborative, and confident
  • Experience with ARM-based SoCs
  • Familiarity with design static checks like CDC, RDC, CLP
  • Hands-on experience with chip IO integration
  • Working knowledge of GIT is a plus

Tools you’ll be using include:

  • Synopsys/Cadence Tools
  • Design Compiler
  • SpyGlass Tools
  • Python

Preferred Qualifications:

We value not just technical excellence, but also collaboration and inclusivity:

  • Strong communication, collaboration, and teamwork skills—especially in diverse and inclusive environments
  • Experience with advanced peripheral bus IPs such as GPIO, UART, SPI, SW, JTAG, and I2C
  • Solid fundamentals in VLSI design
  • Sharp problem-solving and data analysis abilities
  • Proficiency in scripting languages like Perl, TCL, Python
  • Ability to work effectively with remote teams
  • A data-driven mindset to influence tools, flows, and design methodologies for construction, signoff, and optimization.

 

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Company

Capgemini

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