Staff Engineer, Design Verification Engineering

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY22 and approximately 25,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible.

Employer:                    Analog Devices, Inc.  

Job Title:                     Staff Engineer, Design Verification Engineering

Job Requisition:         R243320 

Job Location:              Durham, North Carolina

Job Type:                    Full Time

Rate of Pay:                 $131,144.00 - $185,250.00 per Year

Duties:                        

Perform RTL and gate-level simulation debug and analysis. Implement state-of-the-art mixed-signal technology radio-frequency (“RF”) Transceiver chips. Collaborate with design teams and software/firmware development teams to capture the intended operation and configuration of the system. Develop SystemVerilog UVM simulation environments, infrastructure, and verification plans at both full chip and lock level. Perform design verification using UVM methodologies. Verify logic circuit functionality by writing test-benches and regression tests at both the full chip and block level. Develop system-level test cases using ARM and/or RISC-V processors. Create, simulate, and debug constrained random and directed cases based on the verification plans. Create verification IP and enhance verification methodologies. Write functional coverage, simulation assertions, formal assertions, and other metrics to track progress and completeness of verification effort. Conduct regressions analyses, including debugging of circuit failures in regression testing. Run structural simulations with post-layout timing information. Measure and analyze coverage results and take necessary actions to fill the coverage gaps. Partial telecommute benefit (2 days WFH).

Requirements:                 

Master’s degree in Electrical Engineering or a related field (willing to accept a foreign education equivalent) and 3 years of experience as a Verification Engineer, designing, reviewing and implementing SystemVerilog and Universal Verification Methodology (UVM) test benches and tests.

Special Skills:       

Must also possess the following (quantitative experience requirements not applicable to this section):
• Demonstrated Expertise (DE) architecting and debugging Universal Verification Methodology (UVM) chip level and block level test benches, writing SystemVerilog Assertions, and analyzing and debugging failures in Register Transfer Level (RTL) and X propagation simulations using tools such as Synopsys Verdi;
• DE developing C++ test cases and debugging using tools such as Tarmac debugger;
• DE verifying multiple bus protocols in ARM processor based chips, using knowledge of protocols such as APB, PCIe Gen 4, NVMe, AXI4, and DDR4;
• DE verifying scalable datacenter processor chips and intellectual property (IP)s used in Augmented/Virtual Reality chips; and
• DE in code and functional coverage closure using the Synopsis Verdi coverage tool.  

Contact: Eligible for Employee referral program. Apply online at https://www.analog.com/en/careers.html and reference job R243320 .

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

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