Intern, Digital Design - Summer 2025

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor’s 30-year legacy of technology advancements and strong IP portfolio but with a new mission—to enhance Murata’s world-class capabilities with high-performance semiconductors. With a strong foundation in RF integration, pSemi’s product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi’s team explores new ways to make electronics for the connected world smaller, thinner, faster and better.

Intern, Digital Design

 

Job Summary

The Intern Digital Engineer is a part of the Digital Engineering team within the Engineering Infrastructure Department. At pSemi, we are looking for an enthusiastic and motivated Digital Design Intern to join our team. The ideal candidate for this position will be a high-performing BS, MS or PHD student in Electrical Engineering or Computer Science who has a passion for technology and enjoys working in a fast-paced and dynamic environment.

 

We are seeking a self-starter who is eager to learn and can think critically and work independently. In this role you will have the opportunity to gain valuable experience in the development of standard cell libraries, digital place for related process. To be successful in this role, you should have a strong understanding of circuit and layout design fundamentals and be comfortable with scripting languages. In addition, excellent organizational and communication skills are essential.

 

Roles & Responsibilities

This position has responsibility for:

• Learn in the development Standard cell library development including circuit and architecture optimization for power, performance, and area optimization.
• Utilize scripting languages to develop and optimize standard cell libraries. Apply digital design fundamentals to optimize standard cell libraries.
• Develop and test new design and layout techniques for standard cell libraries. Maintain and track library development progress. Research and analyze current industry trends related to standard cell libraries.
• Perform a place and route test case to ensure the routing ports are accessible.
• Collaborate with other team members to ensure library development is completed in a timely manner.
• Create and document test plans and procedures to ensure accuracy of library designs.
• Generate reports and presentations for internal and external use. Identify areas of improvement and suggest solutions.
• Supporting development and delivery for various processes and PDK (process design kits) test-chips and benchmarking standard cells content.
• Flow automation skills in standard cells, development, and integration to improve execution efficiency. Experience of using TCL/Python/Perl

Minimum Qualifications (Experience and Skills)

• Knowledge with transistor level circuit design using Cadence Virtuoso and circuit simulator such as SPECTRE, SPICE
• An understanding of transistor level device physics and standard cell layout parasitic and knowledge of power, performance, and area tradeoffs