Senior Member of Technical Staff (#91071)

Responsible for the architecture, design, and performance analysis of core design of anaccelerator on a System on a chip meant to accelerate key portions of the software stack in thedata center.  Responsible for modeling key characteristics of workload and architecture andmicroarchitecture in a cycle accurate model. Responsible for the optimization of workload anddesign and provide feedback to architecture team and microarchitecture team to improveperformance. Suggest various optimizations to the design through modeling and analysis. Evaluate performance, power, and area tradeoffs to maximize efficiency of the design.   Work toimprove original workload with feedback from performance analysis and architect an end to endsolution for high performance algorithms to run on the data center. Responsible for the analysisof algorithms, profiling of workloads and generating ideas to accelerate the functions acrossSW/HW and then model those ideas in a cycle accurate model, demonstrating performancegains and then driving the idea into the design with a spec, assisting with hardware definitionand then driving the idea to closure with performance analysis to make sure the gains are asexpected when implemented in silicon.

Education:

• Master’s or foreign equivalent in Electrical Engineering, Computer Engineering, or related field

Experience:

• 2 years of experience in job offered or related occupation.

Special Requirements: Must have prior coursework or project experience in each of the following::

• Carrying out low-power static checks and low-power simulations of a graphics processor at RTL to verify low-power features such as power-gating and clock-gating.
• Providing power aware functional verification of the Tegra product-family mobile application processors.
• Developing a PERL script based utility to convert an in-house power specification to UPF (IEEE Std. 1801-2009).
• Debugging test failures resulting from incorrect power specification in design.
• Synopsys Multi Voltage Rule Checker, Synopsys Multi Voltage Simulator, UPF (IEEE 1801), Synopsys VCS, and Verilog HDL.
**Telecommuting allowed for this position**

Worksite: 3315 Scott Blvd., Floor 4, Santa Clara, CA 95054 Applicant Instructions: Email resume to: jen@rivosinc.com. Include job code 91071 in reply. EOE.