Director, Embedded Memory

<h3>Company Description</h3><p><strong><strong>About Silvaco: </strong></strong>Silvaco is a publicly traded company on the Nasdaq market under the symbol SVCO. For over three decades, Silvaco, based in Silicon Valley, California and with global locations around the world has solved semiconductor design challenges by offering affordable and competitive TCAD (Technology Computer Aided Design) software, EDA (Electronic Design Automation) software, proven design IP (intellectual property), and world class support to engineers and researchers across the globe. Silvaco solutions span from atoms to systems: starting with simulation of material behavior impacting semiconductor devices, to design and analysis of transistor circuits, and lastly providing IP blocks for systems-on-chip (SoC) designs.  </p><h3>Job Description</h3><p><strong>About the Role </strong></p><p>This role is based in the country of France (hybrid office).</p><p>Silvaco is hiring a Memory Design Lead to drive the architecture, design, customer interface and delivery of our embedded memory compiler portfolio: single-port SRAM, ROM, single- and dual-port register files (1PRF, 2PRF), and dual-port RAM (DPRAM). You will lead a team of memory designers, set the technical direction across multiple process nodes, and serve as the senior technical voice in customer engagements — from early presales architecture discussions through PPA negotiation, integration support, and silicon qualification. </p><p>This role blends deep technical leadership with direct customer impact. You will shape what our compilers can do, how competitive their PPA is, and how confidently our customers can integrate them into their SoCs. If you have built memory compilers in production, mentored design teams, and enjoy translating customer requirements into winning silicon, this is a high-leverage role at a fast-growing semiconductor IP and EDA company. </p><p><strong>Key Responsibilities </strong></p><p><strong>Technical Leadership &amp; Memory Design </strong></p><ul><li><p>Lead architecture, circuit design, and physical implementation of memory compilers across SRAM, ROM, 1-port and 2-port register files, and dual-port RAM. </p></li></ul><ul><li><p>Define bitcell selection, peripheral architecture (decoders, sense amps, write drivers, IO, self-timing), redundancy and repair strategy, and assist circuits (read/write assist, body bias) to hit aggressive PPA targets. </p></li></ul><ul><li><p>Drive Vmin, leakage, performance, area, and yield optimization across PVT corners, process variation, and aging effects. </p></li></ul><ul><li><p>Own the technical roadmap for the memory portfolio: new compiler variants, new nodes, feature enhancements, and methodology improvements. </p></li></ul><ul><li><p>Establish design, verification, and signoff methodology, while leading design and layout reviews, SPICE/FastSPICE characterization, statistical/Monte Carlo analysis, BIST/repair, DFT, and physical verification. </p></li></ul><ul><li><p>Lead silicon validation efforts including test chip development, testing and reporting.  </p></li></ul><p><strong>Team Leadership </strong></p><ul><li><p>Lead, mentor, and grow a team of memory design engineers spanning circuit design, layout, characterization, and compiler/automation. </p></li></ul><ul><li><p>Set individual and team goals, conduct technical reviews, and develop career paths for engineers at multiple levels. </p></li></ul><ul><li><p>Allocate engineering effort across roadmap projects, customer commitments, and silicon programs; manage schedules, dependencies, and risk. </p></li></ul><ul><li><p>Build a culture of design rigor, peer review, and continuous methodology improvement. </p></li></ul><p><strong>Presales &amp; Customer Engagement </strong></p><ul><li><p>Serve as the senior technical lead in presales engagements — qualifying opportunities, presenting Silvaco's memory portfolio, and shaping winning technical proposals. </p></li></ul><ul><li><p>Translate customer SoC requirements (frequency, voltage, density, power, port configuration, special modes) into compiler specifications and PPA commitments. </p></li></ul><ul><li><p>Partner with sales, field application engineers, and product management on RFQs, technical evaluations, and competitive benchmarking. </p></li></ul><ul><li><p>Lead deep-dive technical workshops with customer architects and design teams; respond to detailed technical questionnaires and audit-style reviews. </p></li></ul><p><strong>PPA Analysis &amp; Benchmarking </strong></p><ul><li><p>Own PPA analysis across the memory portfolio — performance, power (active and leakage), area, and yield — at both the instance and SoC-aggregate level. </p></li></ul><ul><li><p>Build and maintain competitive benchmarks against foundry and third-party memory IP; identify gaps and prioritize closure. </p></li></ul><ul><li><p>Drive what-if and sensitivity analysis to guide architecture trade-offs (e.g., bitcell choice, mux ratio, banking,