Principal Mixed Signal Design Verification Engineer

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p> </p> <p><strong>Job Description</strong></p> <p>We are looking for Principal Design Verification Engineers with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.</p> <p><strong>Basic qualifications:</strong></p> <ul> <li>Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is<br>required, and a Maser’s is preferred.</li> <li>≥8 years’ experience supporting or developing complex high-speed SerDes/silicon products for Server, Storage, and/or<br>Networking applications.</li> <li>Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for<br>customer meetings in advance, and to work with minimal guidance and supervision.</li> <li>Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!</li> <li>Authorized to work in US and start immediately.</li> </ul> <p><strong>Required Experience</strong></p> <ul> <li>Experience with integrating Matlab/Simulink/C/C++ in System Verilog environments using DPI/PLI</li> <li>Ability to use scripting tools (Perl/Python) to automate verification infrastructure.</li> <li>Experience in developing infrastructure and tests in a hybrid directed and