Sr. Staff SOC Verification Engineer

General Information

Job Title Sr. Staff SOC Verification Engineer Job ID 9981 City US (non-CA) Off-Site State/Province US (non-CA) Off-Site Office Date Posted 06-Mar-2025 Job Category Engineering Job Subcategory SOC Engineering Hire Type Employee Remote Eligible No Base Salary Range: $116000 - $175000

Descriptions & Requirements

Job Description and Requirements

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and experienced SoC Verification Engineer who thrives in a dynamic and collaborative environment. You possess a strong background in ASIC verification, with a particular emphasis on designing and writing constrained-random SystemVerilog testbenches using UVM. You have a keen eye for detail and take pride in ensuring that every design meets the highest standards of quality and performance. Your technical expertise is complemented by your ability to mentor and guide less experienced team members, fostering a culture of continuous learning and improvement. You are adept at debugging RTL and GLS failures, and your problem-solving skills are second to none. Your communication skills enable you to effectively convey complex technical concepts to both technical and non-technical stakeholders. You are committed to staying abreast of the latest industry trends and technologies, and you are eager to contribute to the development of next-generation, high-performance ASICs.

What You’ll Be Doing:

• Defining and tracking Verification test plans

• Designing and writing constrained-random SystemVerilog testbenches using UVM

• Writing SystemVerilog assertions

• Writing functional coverage

• Debugging RTL and GLS failures

• Conducting code coverage analysis

• Providing mentoring and guidance to less experienced team members

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