Sr. Staff Engineer, Timing Methodology & Signoff

<div class="content-intro"><p><span style="font-size: 12pt;"><strong>Company Overview</strong></span></p> <p><strong>Ambiq</strong>&nbsp;is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.</p> <p>Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.</p> <p>Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.</p> <p>We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.</p> <p>At Ambiq, we live by five values:&nbsp;<strong>Innovate. Collaborate. Focus. Learn. Achieve.</strong></p> <p>If that's you, join us — the intelligence everywhere revolution starts here.</p> <p>&nbsp;</p></div><div> <h3><strong>Build the silicon that powers the future of ultra-low-power computing</strong></h3> <p>At Ambiq, we’re redefining what’s possible at the edge—powering next-generation AI, wearables, and IoT devices with breakthrough ultra-low-power technology. We’re looking for a <strong>Sr. Staff Engineer – Timing Methodology</strong> to take a <strong>true ownership role</strong> in driving timing from architecture to silicon—and ensuring our designs don’t just work, but <em>excel</em> in real-world conditions.</p> <hr> <h2><strong>Why this role stands out</strong></h2> <p>This isn’t a “maintain the flow” role. You’ll:</p> <ul> <li>Own <strong>end-to-end timing convergence</strong> (block → SoC → post-silicon)</li> <li>Shape <strong>methodology, flows, and signoff strategy</strong></li> <li>Work on <strong>cutting-edge FinFET, multi-patterning nodes</strong>, and unique ultra-low-power challenges</li> <li>Directly influence <strong>PPA and product success</strong></li> </ul> <p>If you thrive on solving complex timing problems others shy away from—this is your playground.</p> <hr> <h2><strong>What You’ll Do</strong></h2> <ul> <li><strong>Own timing convergence end-to-end</strong>, from methodology de