Senior Avionics PCB Layout Engineer - TeraWave

Application close date:

Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!  

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Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. 

As part of the Spacecraft Bus Avionics team, you will be responsible for complex PCB layouts with Field Programmable Gate Arrays (FPGA) at the core for vehicle control and operation with processing and integration of various system interfaces. As part of the development team, you will design, develop, and verify high-performance avionics hardware for space flight vehicles. You will drive requirements definition, modeling, analysis, design, test, and production release of on-vehicle systems. Your responsibilities will encompass electronic requirements, architecture concepts, detailed design development, design verification and test. In addition, you will follow avionics designs through formal verification, environmental qualification, release, and participate in integration and flight support activities.

Responsibilities include but are not limited to:

• Design multi-layer PCBs for complex digital, mixed-signal and high power systems including FPGAs, Microcontrollers
• Develop PCB layouts for Digital/Analog/RF circuits with careful attention to impedance control, loss tangent, and electromagnetic compatibility
• Perform signal integrity analysis for high-speed digital interfaces (PCIe, DDR, Ethernet)
• Conduct power integrity analysis and design power distribution networks (PDN) for low-noise, high-current applications
• Create component libraries, design rule checks (DRCs), and maintain design standards
• Collaborate with electrical engineers on component selection, schematic review, and design optimization
• Generate fabrication and assembly documentation including Gerber files, drill files, and assembly drawings
• Work with PCB fabricators and CM vendors to ensure manufacturability and resolve fabrication issues
• Support board bring-up activities, debugging hardware issues related to PCB design
• Design for space environment considerations including thermal management, radiation tolerance, and mechanical stress

Minimum Qualifications:

• B.S. in Electrical Engineering, Computer Engineering, or related field with 5+ years of PCB design experience
• Proficiency with PCB design tools (Altium Designer, Cadence Allegro, or similar)
• Strong understanding of signal integrity principles for high-speed digital design (transmission lines, termination, crosstalk)
• Experience with controlled impedance design and working with PCB stackup optimization
• Experience with high voltage layout design including considerations for creepage clearance and thermal management.
• Knowledge of EMI/EMC best practices and design guidelines
• Familiarity with IPC standards (IPC-2221, IPC-6012, IPC-A-610)
• Experience with PCB layout for FPGAs, high-speed ADCs/DACs, or mixed-signal designs

Preferred Qualifications;

• Experience with RF/microwave PCB design using high-frequency laminates (Rogers, Taconic, etc.)
• Knowledge of power integrity analysis tools (e.g., HyperLynx, Ansys SIwave, Cadence Sigrity)
• Familiarity with thermal analysis tools and thermal management techniques for high-power electronics
• Experience designing for space environment (vacuum, thermal cycling, radiation, vibration)
• Understanding of design for manufacturing (DFM) and design for test (DFT) principles
• Knowledge of conformal coating, potting, and other space-qualification techniques
• Previous experience with aerospace or satellite PCB designs
• Familiarity with MIL-STD or NASA standards for PCB design

 

Compensation Range for:

CA applicants is $156,802.00 - $219,522.45 CO applicants is $144,179.00 - $201,849.90 WA applicants is $156,802.00 - $219,522.45

Other site ranges may differ

Culture Statement

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