Senior Digital Validation Engineer

Secure Transactions and Identification (STI) works at the forefront of technology providing solutions for mobile wallet (payment, transit, access), mobile security, and UWB in consumer products ranging from wearables, smart phones to laptops.

STI Digital Validation team is responsible for ensuring the functionality, performance, and robustness of SoC devices across pre‑silicon and post‑silicon phases. We are seeking a Senior Digital Validation Engineer to work at San Diego location with deep SoC validation experience and a passion for ARM and RISC‑V based architectures, low‑level software development, hands‑on lab bring‑up, scalable validation automation, and standard SoC communication interfaces.

In this role, you will take technical ownership of validation efforts, lead complex system‑level debug, and design automation solutions that enable efficient, repeatable silicon validation.

Key Responsibilities

• Own and drive block‑level and system‑level validation strategy, including validation scope, coverage, and test planning

• Perform deep analysis of specifications and system use cases to ensure complete functional, performance, and interface coverage

• Review validation strategies with key stakeholders, including design leads, system teams, and architects

• Implement and maintain validation test infrastructure using C and Java

• Validate interface functionality, performance, power behavior, and corner cases across operating modes

• Lead validation on pre‑silicon platforms, such as FPGA emulation

• Execute and guide post‑silicon validation campaigns, including silicon bring‑up, evaluation, and characterization

• Perform hands‑on lab validation using oscilloscopes, advanced power supplies, DMMs, source meters (SMUs), waveform generators, and temperature controllers

• Design and implement automation solutions for validation workflows, including:

  • Automated test execution and sequencing

  • Instrument control and configuration

  • Data collection, analysis, and reporting

  • Regression testing across silicon revisions

• Develop automation primarily using Python, integrating low‑level C test code with higher‑level control frameworks

• Drive complex hardware/software co‑debug, including root‑cause analysis of interface, protocol, and timing‑related issues

• Mentor junior engineers and provide technical leadership in validation and automation best practices

Required Qualifications

• Master’s degree in Computer Science, Computer Engineering, Electrical Engineering

• At least 5 years of industry related experience

• Strong professional experience in SoC digital validation

• Extensive experience with embedded C programming with either ARM or RISCV based microcontrollers.

• Proficiency in at least one object‑oriented programming language (Java, C++, C#, etc.)

• Strong experience with automation and scripting, preferably Python

• Hands‑on experience validating SoC communication interfaces such as  I2C / I3C, SPI, SPMI, ISO‑UART (7816)

• Strong hands‑on lab experience with electrical measurement and control equipment, including:

  • Oscilloscopes

  • Programmable power supplies

  • DMMs

  • Source meters (SMUs)

  • Waveform / signal generators

  • Temperature / thermal controllers

• Proven ability to debug complex issues across protocol, hardware, firmware, and system levels

• Strong sense of ownership, technical judgment, and attention to detail

Preferred Qualifications (Nice to Have)

• Background in design verification or close collaboration with DV teams

• Experience with post‑silicon logic debug, including deep analysis of test logs

• Experience developing software hooks or firmware instrumentation for debug

• Familiarity with ARM‑ or RISC‑V‑based SoC architectures and system bring‑up

• Experience improving validation workflows through automation, regression frameworks, or lab infrastructure standardization

Why Join This Role

• Senior‑level ownership with direct impact on silicon readiness and product quality

• Strong emphasis on hands‑on lab work, block level and system level validation, interface validation, and automation

• Opportunity to influence validation methodology and tooling