ASIC Power Implementation Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 5 years of experience with digital design, specializing in power implementation, and developing methodologies and flows for chips with multiple IPs and hierarchical partitions.
• Experience using EDA tools like VCLP, Conformal LP, Power-Artist, PT/PTPX, Incisive/VCS.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience in low power digital ASIC design including UPF/CPF, multi-voltage domains, power gating and on chip power management.
• Experience in design and analysis of power management IPs with a solid understanding of clock, reset, and power sequencing interactions.
• Experience in post-silicon validation and debug.
• Experience with gate-level SPICE simulations and statistical SPICE models.
• Excellent scripting skills in Tcl, Perl, or Python.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Define and drive power methodology for design, verification, and implementation of silicon.
• Develop innovative schemes to achieve power reduction from circuit to system level.
• Develop methodology and tools for implementing power reduction. Work with tool vendors to address any power-related tool or flow issues.
• Work with architects and logic designers to understand the power requirements and define all power specs and budgets.
• Estimate power for blocks and top-level using EDA tools and roll-up full-chip power.