Senior ASIC Verification Engineer

<h2>SENIOR ASIC VERIFICATION ENGINEER</h2> <p><span>We are seeking a motivated, detail-oriented engineer with:</span></p> <ul> <li><span>Strong analytical and problem-solving skills</span></li> <li><span>A proactive mindset and eagerness to learn</span></li> <li><span>A solid foundation in ASIC verification methodologies4</span></li> <li><span>The drive to grow and contribute to high-impact projects</span></li> </ul> <p><span>At Capgemini, we foster a collaborative and supportive environment where innovation thrives. You will have the opportunity to:</span></p> <ul> <li><span>Work on exciting, industry-leading projects</span></li> <li><span>Expand your skills with continuous learning</span></li> <li><span>Make meaningful contributions from day one</span></li> </ul> <p><span>If you're ready to grow your expertise and make a difference in a fast-paced, forward-thinking team, <strong>we encourage you to apply!</strong></span></p> <p> </p><h2>KEY RESPONSIBILITIES</h2> <p> </p> <ul type="disc"> <li>Proficiency in UVM, SystemVerilog, and C/C++</li> <li>Experience with SystemVerilog simulators and waveform debuggers</li> <li>Hands-on experience in SystemVerilog test bench development, including:</li> <li>Strong debugging and analytical skills, with the ability to identify issues in architecture, functionality, and performance</li> <li>Stimulus generation</li> <li>Checkers, assertions, scoreboarding</li> <li>Transactors/BFMs</li> <li>Functional coverage and cover points</li> </ul><h2>ACADEMIC CREDENTIALS</h2> <p> </p> <ul type="disc"> <li>BSEE or equivalent. MSEE preferred</li> </ul>