Member of Technical Staff Ref #90393

Responsible for building a high-performance memory controller as part of the DDR5 memory controller IP design verification team. Verify that designs conform to all requirements of the JEDEC DDR5 DIMM specification while also ensure that designs are functionally correct and meet complex reliability, availability, serviceability, latency, and bandwidth requirements. Develop test plans for all features in these controllers, and execute these test plans through implementing UVM-based verification environments in the system Verilog hardware description language that include creating monitors, scoreboards, and stimulus sequences. Debug the design microarchitecture for any failing simulations followed by coverage analysis of the testcase suite to ensure that all areas of the design have been tested. Help with creating a verification environment for testing the controller to a third party emulation platform where 

Education

• Bachelor’s or foreign equivalent in Electrical Engineering, Electronics Engineering, or related field

Experience

• 5 years of progressive experience in job offered or related occupation

Special Requirements: Must have at least 1 year of prior work experience in each of the following

• 1. Writing configurable DDR testbench in UVM using multiple AXI VIP for data ports, AHB VIP for register port and Denali DDR VIPs to support DDR4 and LPDDR4. Building configurable agent with monitors and a basic scoreboard to compare end-to-end data.
• 2. Verification of STM and DPU blocks that are used in the next generation of Intel Tofino Fabric Processor. Building formal testbench from scratch, writing end-to-end SVA check using various abstraction techniques.
• 3. Bringing up DDR controller on palladium using MMP models and debugging any related failures during Linux boot.
• 4. Writing reusable code load various memories (SRAM, TCM, DDR, etc.) using MARG APIs.
• 5. Developing a UVM base AVIP for JTAG by writing a new synthesizable BFM and reusing the UVM part of the existing JTAG VIP.
• 6. Verification of DDR Controller for ASIL-B and ASIC-C certification by verifying many features like FIFO protection logic, Multi ECC Errors, Logic Replication, etc.
*Experience must be progressively responsible* **Telecommuting allowed 

Worksite: 6433 Champion Grandview Way, Build 2, Suite 150, Austin TX 78750Applicant Instructions: Include job code 90393 in application. EOE