Senior Leader, Electrical & Optical Systems Engineer

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > Packaging Engineering

General Summary:

Qualcomm Central Hardware Systems (CHS) team is seeking a Senior Leader, Electrical & Optical Systems Engineer to define, develop, and productize next-generation electrical and optical interconnect technologies for AI, hyperscale datacenter, networking, and HPC systems.

The successful candidate will be a recognized technical leader with deep expertise in 224G/448G SerDes, electrical-optical system co-design, SI/PI, DSP algorithms, EIC/PIC integration, optical networking, advanced packaging, and end-to-end system architecture. This role spans silicon, photonics, packaging, PCB, flyover interconnects, optics, and rack-scale infrastructure.

Key Responsibilities:

• Define and drive end-to-end architecture for next-generation interconnect solutions utilizing 112G, 224G, and emerging 448G SerDes technologies, Co-Packaged Optics (CPO), Near-Packaged Optics (NPO), Linear Pluggable Optics (LPO), Co-Packaged Connectors (CPC), Near-Package Connectors (NPC), copper and optical flyover architectures, Active Electrical Cables (AEC), and advanced optical interconnects.
• Lead system design and performance closure across SerDes and PHY architectures, EIC/PIC integration, optical engines, transceiver subsystems, advanced package substrates, PCB channels, connectors, cables, optics, power delivery, thermal, and mechanical architectures.
• Own SI/PI methodology and end-to-end link analysis including channel budgeting, COM analysis, jitter, crosstalk, insertion loss, return loss, equalization strategy, and simulation-to-silicon correlation.
• Drive electrical-optical DSP architecture and algorithm development including TX/RX equalization, CDR, adaptive filtering, FEC, impairment compensation, channel optimization, and overall system performance analysis.
• Develop system-level models and architecture tradeoff studies spanning bandwidth, reach, power, latency, reliability, manufacturability, cost, and scalability.
• Provide technical leadership across silicon, package, optics, platform, and software organizations while driving technology roadmaps and productization from concept through deployment.

Qualifications:

• Demonstrated success productizing 112G and/or 224G PAM4 electrical and optical communication systems.

Technical Expertise:

Deep expertise in:

• High-speed SerDes architectures
• Electrical-optical DSP algorithms
• PAM4 communication systems
• Signal Integrity (SI) and Power Integrity (PI)
• EIC/PIC co-design and heterogeneous integration
• Optical transceivers and optical engines
• Co-packaged and near-packaged optics
• Advanced packaging, PCB, connector, cable, CPC, NPC, and flyover technologies
• End-to-end system modeling and architecture
• AI networking, scale-up, and scale-out infrastructures
• Hands-on experience with: ADS, HFSS, CST, HSPICE, MATLAB, Python, Cadence Sigrity, Lumerical, Zemax, Verilog-A, SystemVerilog, COM analysis tools, IBIS-AMI modeling

Preferred Qualifications

• MS or PhD in Electrical Engineering, Optical Engineering, Physics, or a related discipline.
• 15+ years of experience developing high-speed communication, networking, or optical interconnect products.
• Experience developing and productizing 224G+ electrical and optical interconnect solutions.
• Experience with CPO, NPO, CPC, NPC, flyover copper, flyover optical, silicon photonics, and EIC/PIC integration.
• Familiarity with Ethernet, PCIe, UALink, NVLink, OIF CEI, IEEE 802.3, and emerging AI interconnect standards.
• Experience with chiplets, UCIe, silicon photonics, 2.5D/3D integration, and advanced packaging technologies.
• Track record influencing industry standards, technology roadmaps, and large cross-functional architecture decisions.
• Proven success leading and mentoring senior technical teams across multiple engineering disciplines.

Minimum Qualifications:

•    Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 10+ years of System/Package Design/Technology Engineering or related work experience.